I have answered questions of one group of students in the laboratory where to locate interrupts and signals to process the second "dcsimpledrv" IRC signals in software. The IRC related signals are routed to the Zynq Processing System IP EMIO (GPIO from PL) signals. There is an excerpt from complete document with all signals and registers description which I have provided with the design. Routing of IRC signals to the EMIO GPIO port Mapping is provided by canbench_cc_gpio.vhd GPIO0 IRC1_A GPIO1 IRC1_B GPIO2 IRC1_IRQ (external incoming IRQ signal) GPIO3 IRC1_CGH (10 ns pulse when change is detected by qcounter_nbit.vhdl component) GPIO4 IRC2_A GPIO5 IRC2_B GPIO6 IRC2_IRQ (external incoming IRQ signal) GPIO7 IRC2_CGH (10 ns pulse when change is The important information for processing is that the same GPIO (EMIO) peripheral is used for the first and the second IRC input. This means that the same IRQ vector is/has to be used for both IRC inputs processing in the software. But external signal which notifies hardware about IRC signals state change is fed to GPIO6 for the second IRC instead of GPIO2. This means that bit 6 instead of (or together with) bit 2 has to be monitored and unmasked in Interrupt Enable/Unmask register and all other coresponding locations. Best wishes, Pavel Pisa