Cituji Jiri Hubacek <hubacji1@fel.cvut.cz>:
On 01/15/2018 07:20 PM, beranj25@fel.cvut.cz wrote:
I discovered the cause is multiple generated interrupts from GPIO module.
This condition in the beginning of ISR fixes the issue:
#define GPIO_INT_STAT_2 (*(volatile uint32_t *) (ZYNQ7K_GPIO_BASE + 0x00000298)) [...] if (!(GPIO_INT_STAT_2 & 0x4)) { /* Not interrupt from IRC */ return; }
However, I still wonder where are these others interrupts come from.
Multiple HW components are connected to interrupt #52 [1]. If you would like to enable only one GPIO to generate interrupt it should be sufficient to disable all by writing 0xffffffff to INT_DIS bank control in irc_init():
*(volatile uint32_t *) (ZYNQ7K_GPIO_BASE + 0x00000294) = 0xffffffff;
Maybe reset them too:
*(volatile uint32_t *) (ZYNQ7K_GPIO_BASE + 0x00000298) = 0xffffffff;
And then enable only the desired one:
*(volatile uint32_t *) (ZYNQ7K_GPIO_BASE + 0x00000290) = 0x4;
Yeah, that's exactly what I've done.
To be sure, I disabled interrupts from all GPIO banks in irc_init() function, but there are still many of them.
What you mean?
I mean that disabling and resetting interrupts (in this order) wasn't enough to prevent triggering other interrupts on IRQ #52 (GPIO's).
# References [1]: TRM, pg. 389
Have a nice day, Jiri Hubacek
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