--- app/arm/{nazdar1311 => ahoy1311}/Makefile | 0 app/arm/{nazdar1311 => ahoy1311}/Makefile.omk | 9 +- app/arm/ahoy1311/ahoy.c | 30 + app/arm/{nazdar2364 => ahoy2364}/Makefile | 0 app/arm/{nazdar2364 => ahoy2364}/Makefile.omk | 6 +- .../nazdar2364.c => ahoy2364/ahoy2364.c} | 0 app/arm/nazdar1311/nazdar.c | 32 - app/arm/nazdar1311/uart.c | 101 -- app/arm/nazdar1311/uart.h | 47 - arch/arm/{mach-lpc_m3 => mach-lpc13xx}/Makefile | 0 .../arm/{mach-lpc_m3 => mach-lpc13xx}/Makefile.omk | 0 .../{mach-lpc_m3 => mach-lpc13xx}/defines/Makefile | 0 .../defines/Makefile.omk | 0 .../defines/core_cm3.h | 0 .../defines/lpc13xx-arm.h} | 986 ++++++++++---------- arch/arm/mach-lpc13xx/defines/lpc13xx.h | 81 ++ arch/arm/mach-lpc13xx/defines/lpc2xxx.h | 2 + .../{mach-lpc_m3 => mach-lpc13xx}/libs/Makefile | 0 .../libs/Makefile.omk | 0 .../libs/boot/Makefile | 0 .../libs/boot/Makefile.omk | 0 .../libs/boot/crt0_13xx.c | 18 +- .../libs/boot/initarray.c | 0 .../libs/ldscripts/Makefile | 0 .../libs/ldscripts/Makefile.omk | 0 .../mach-lpc13xx/libs/ldscripts/lpc1311.ld-flash | 19 + .../libs/ldscripts/lpc1311.ld-ram | 0 .../libs/ldscripts/lpc13xx-flash.ld} | 24 +- .../libs/ldscripts/lpc13xx-ram.ld | 0 .../{mach-lpc23xx => mach-lpc13xx}/libs/uart_zen | 0 arch/arm/mach-lpc13xx/tools/lpcchksum/lpcchksum.sh | 6 + arch/arm/mach-lpc21xx/libs/uart_zen/uart_zen.c | 19 +- board/arm/lpc1311-mini/config.lpc1311-mini | 6 +- 33 files changed, 681 insertions(+), 705 deletions(-) rename app/arm/{nazdar1311 => ahoy1311}/Makefile (100%) rename app/arm/{nazdar1311 => ahoy1311}/Makefile.omk (51%) create mode 100644 app/arm/ahoy1311/ahoy.c rename app/arm/{nazdar2364 => ahoy2364}/Makefile (100%) rename app/arm/{nazdar2364 => ahoy2364}/Makefile.omk (64%) rename app/arm/{nazdar2364/nazdar2364.c => ahoy2364/ahoy2364.c} (100%) delete mode 100644 app/arm/nazdar1311/nazdar.c delete mode 100644 app/arm/nazdar1311/uart.c delete mode 100644 app/arm/nazdar1311/uart.h rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/Makefile (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/Makefile.omk (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/defines/Makefile (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/defines/Makefile.omk (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/defines/core_cm3.h (100%) rename arch/arm/{mach-lpc_m3/defines/lpc13xx.h => mach-lpc13xx/defines/lpc13xx-arm.h} (97%) create mode 100644 arch/arm/mach-lpc13xx/defines/lpc13xx.h create mode 100644 arch/arm/mach-lpc13xx/defines/lpc2xxx.h rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/Makefile (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/Makefile.omk (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/boot/Makefile (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/boot/Makefile.omk (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/boot/crt0_13xx.c (97%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/boot/initarray.c (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/ldscripts/Makefile (100%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/ldscripts/Makefile.omk (100%) create mode 100644 arch/arm/mach-lpc13xx/libs/ldscripts/lpc1311.ld-flash rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/ldscripts/lpc1311.ld-ram (100%) copy arch/arm/{mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld => mach-lpc13xx/libs/ldscripts/lpc13xx-flash.ld} (91%) rename arch/arm/{mach-lpc_m3 => mach-lpc13xx}/libs/ldscripts/lpc13xx-ram.ld (100%) copy arch/arm/{mach-lpc23xx => mach-lpc13xx}/libs/uart_zen (100%) create mode 100755 arch/arm/mach-lpc13xx/tools/lpcchksum/lpcchksum.sh diff --git a/app/arm/nazdar1311/Makefile b/app/arm/ahoy1311/Makefile similarity index 100% rename from app/arm/nazdar1311/Makefile rename to app/arm/ahoy1311/Makefile diff --git a/app/arm/nazdar1311/Makefile.omk b/app/arm/ahoy1311/Makefile.omk similarity index 51% rename from app/arm/nazdar1311/Makefile.omk rename to app/arm/ahoy1311/Makefile.omk index 3da5a76..bcb90da 100644 --- a/app/arm/nazdar1311/Makefile.omk +++ b/app/arm/ahoy1311/Makefile.omk @@ -1,11 +1,12 @@ # -*- makefile -*- -ifeq ($(MACH),lpc_m3) -bin_PROGRAMS = nazdar1311 +ifeq ($(MACH),lpc13xx) +bin_PROGRAMS = ahoy1311 -nazdar1311_SOURCES = nazdar.c uart.c +ahoy1311_SOURCES = ahoy.c +ahoy1311_LIBS = uart_zen -link_VARIANTS = ram +link_VARIANTS = ram flash else ifeq ($(RELATIVE_DIR),$(INVOCATION_DIR)) $(error This works only with LPC13xx machnies!) diff --git a/app/arm/ahoy1311/ahoy.c b/app/arm/ahoy1311/ahoy.c new file mode 100644 index 0000000..ea4d9ea --- /dev/null +++ b/app/arm/ahoy1311/ahoy.c @@ -0,0 +1,30 @@ +/** tiny lpc1311 uart flood demo **/ + +#include <types.h> +#include <lpc13xx.h> +#include <periph/uart_zen.h> + +#define F_CCLK 12000000 +#define F_PCLK F_CCLK + +void uart_write_str(const char *s) { + for ( ; *s; s++) + while(write_UART_data(0, *s)); +} + +int main() { + LPC_SYSCON->SYSAHBCLKDIV = 1; + LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); //enable clock/power for GPIO + + /* enable TxD, RxD pins */ + IOCON_PIO1_6 = IOCON_PIO1_7 = 1; + /* init UART */ + UART_init(0, 38400, F_PCLK, 0 /* unused */); + + for (;;) { + uart_write_str("Lorem ipsum dolor\r\n"); + volatile int u; + for (u = 0; u < 10000; u++); + } +} diff --git a/app/arm/nazdar2364/Makefile b/app/arm/ahoy2364/Makefile similarity index 100% rename from app/arm/nazdar2364/Makefile rename to app/arm/ahoy2364/Makefile diff --git a/app/arm/nazdar2364/Makefile.omk b/app/arm/ahoy2364/Makefile.omk similarity index 64% rename from app/arm/nazdar2364/Makefile.omk rename to app/arm/ahoy2364/Makefile.omk index 4538b78..69a82ef 100644 --- a/app/arm/nazdar2364/Makefile.omk +++ b/app/arm/ahoy2364/Makefile.omk @@ -1,10 +1,10 @@ # -*- makefile -*- ifeq ($(MACH),lpc23xx) -bin_PROGRAMS = nazdar2364 +bin_PROGRAMS = ahoy2364 -nazdar2364_SOURCES = nazdar2364.c -nazdar2364_LIBS = pwm pll uart_zen +ahoy2364_SOURCES = ahoy2364.c +ahoy2364_LIBS = pwm pll uart_zen link_VARIANTS = ram else diff --git a/app/arm/nazdar2364/nazdar2364.c b/app/arm/ahoy2364/ahoy2364.c similarity index 100% rename from app/arm/nazdar2364/nazdar2364.c rename to app/arm/ahoy2364/ahoy2364.c diff --git a/app/arm/nazdar1311/nazdar.c b/app/arm/nazdar1311/nazdar.c deleted file mode 100644 index 8dde369..0000000 --- a/app/arm/nazdar1311/nazdar.c +++ /dev/null @@ -1,32 +0,0 @@ -/** tiny lpc1311 uart flood demo, taken from Poppik&Tabak git repo **/ - -#include <stdlib.h> -#include <types.h> -#include <lpc13xx.h> -#include <cpu_def.h> - -#include "uart.h" - -int main() { - LPC_SYSCON->SYSAHBCLKDIV = 1; - LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); //enable clock/power for GPIO - - uart_simple_init(38400); - - //set PIO1[0] - PIO1[3] to IO - LPC_IOCON->JTAG_TMS_PIO1_0 &= ~0x7; - LPC_IOCON->JTAG_TMS_PIO1_0 |= 0x1; - LPC_IOCON->JTAG_TDO_PIO1_1 &= ~0x7; - LPC_IOCON->JTAG_TDO_PIO1_1 |= 0x1; - LPC_IOCON->JTAG_nTRST_PIO1_2 &= ~0x7; - LPC_IOCON->JTAG_nTRST_PIO1_2 |= 0x1; - LPC_IOCON->ARM_SWDIO_PIO1_3 &= ~0x7; - LPC_IOCON->ARM_SWDIO_PIO1_3 |= 0x1; - - for (;;) { - uart_simple_send("Lorem ipsum dolor\r\n"); - volatile int u; - for (u = 0; u < 10000; u++); - } -} diff --git a/app/arm/nazdar1311/uart.c b/app/arm/nazdar1311/uart.c deleted file mode 100644 index f896b4d..0000000 --- a/app/arm/nazdar1311/uart.c +++ /dev/null @@ -1,101 +0,0 @@ -#include <lpc13xx.h> -#include "uart.h" - -#define BIT(n) (1 << (n)) - -void uart_simple_init(int baudrate) { - uint32_t Fdiv; - uint32_t regVal; - - LPC_IOCON->PIO1_6 &= ~0x07; /* UART I/O config */ - LPC_IOCON->PIO1_6 |= 0x01; /* UART RXD */ - LPC_IOCON->PIO1_7 &= ~0x07; - LPC_IOCON->PIO1_7 |= 0x01; /* UART TXD */ - - /* Enable UART clock */ - LPC_SYSCON->SYSAHBCLKCTRL |= BIT(12); - LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */ - - LPC_UART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ - regVal = LPC_SYSCON->UARTCLKDIV; - Fdiv = (((IRC_OSC/LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ; /*baud rate */ - - LPC_UART->FDR = 0x10; /* No Fractional Divider */ - LPC_UART->DLM = Fdiv / 256; - LPC_UART->DLL = Fdiv % 256; - LPC_UART->LCR = 0x03; /* DLAB = 0 */ - LPC_UART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ - LPC_UART->MCR = 0x0; /* disable auto-flow controll */ - - /* Read to clear the line status. */ - regVal = LPC_UART->LSR; - - /* Ensure a clean start, no data in either TX or RX FIFO. */ - while ( (LPC_UART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) ); - while ( LPC_UART->LSR & LSR_RDR ) - { - regVal = LPC_UART->RBR; /* Dump data from RX FIFO */ - } - return; -} - -void uart_simple_send(char *str) -{ - char ch; - while ((ch = *str)) - { - if (ch == 0) - break; - uart_simple_send_ch(ch); - str++; - } -} - -void uart_simple_send_ch(char ch) -{ - /* active waiting loop */ - while ( !(LPC_UART->LSR & LSR_THRE) ); - - LPC_UART->THR = ch; -} - -void uart_simple_send_i(int number) -{ - char snum[12]; - snum[11] = 0; - uint8_t i = 10; - - if ( number < 0 ) - { - number *= -1; - snum[i--] = '-'; - } - if ( number == 0 ) - snum[i--] = '0'; - else - while ( number != 0 ){ - snum[i--] = (char)(48 + (number % 10)); - number = number / 10; - } - uart_simple_send(&snum[++i]); -} - -void uart_simple_send_h(uint32_t number) -{ - char snum[9]; - snum[8] = 0; - uint8_t i = 7; - - if ( number == 0 ) - snum[i--] = '0'; - else - while ( number != 0 ){ - snum[i] = (char)(48 + (number % 16)); - if (snum[i] > 57) - snum[i] += 7; - i--; - number = number / 16; - } - uart_simple_send(&snum[++i]); -} - diff --git a/app/arm/nazdar1311/uart.h b/app/arm/nazdar1311/uart.h deleted file mode 100644 index c1b8cb0..0000000 --- a/app/arm/nazdar1311/uart.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef UART_H -#define UART_H - -/* Internal RC oscillator frequency */ -#define IRC_OSC (12000000UL) - -/* Some Uart rubbish */ -#define IER_RBR 0x01 -#define IER_THRE 0x02 -#define IER_RLS 0x04 - -#define IIR_PEND 0x01 -#define IIR_RLS 0x03 -#define IIR_RDA 0x02 -#define IIR_CTI 0x06 -#define IIR_THRE 0x01 - -#define LSR_RDR 0x01 -#define LSR_OE 0x02 -#define LSR_PE 0x04 -#define LSR_FE 0x08 -#define LSR_BI 0x10 -#define LSR_THRE 0x20 -#define LSR_TEMT 0x40 -#define LSR_RXFE 0x80 - -/** Init UART with desired baud-rate, using active-wait. - */ -void uart_simple_init(int baudrate); - -/** Send null-terminated string, using active-wait. - */ -void uart_simple_send(char *str); - -/** Send one character, using active-wait. - */ -void uart_simple_send_ch(char ch); - -/** Send number, using active-wait. - */ -void uart_simple_send_i(int number); - -/** Send number in hexadecimal format, using active-wait. - */ -void uart_simple_send_h(uint32_t number); - -#endif /* UART_H */ diff --git a/arch/arm/mach-lpc_m3/Makefile b/arch/arm/mach-lpc13xx/Makefile similarity index 100% rename from arch/arm/mach-lpc_m3/Makefile rename to arch/arm/mach-lpc13xx/Makefile diff --git a/arch/arm/mach-lpc_m3/Makefile.omk b/arch/arm/mach-lpc13xx/Makefile.omk similarity index 100% rename from arch/arm/mach-lpc_m3/Makefile.omk rename to arch/arm/mach-lpc13xx/Makefile.omk diff --git a/arch/arm/mach-lpc_m3/defines/Makefile b/arch/arm/mach-lpc13xx/defines/Makefile similarity index 100% rename from arch/arm/mach-lpc_m3/defines/Makefile rename to arch/arm/mach-lpc13xx/defines/Makefile diff --git a/arch/arm/mach-lpc_m3/defines/Makefile.omk b/arch/arm/mach-lpc13xx/defines/Makefile.omk similarity index 100% rename from arch/arm/mach-lpc_m3/defines/Makefile.omk rename to arch/arm/mach-lpc13xx/defines/Makefile.omk diff --git a/arch/arm/mach-lpc_m3/defines/core_cm3.h b/arch/arm/mach-lpc13xx/defines/core_cm3.h similarity index 100% rename from arch/arm/mach-lpc_m3/defines/core_cm3.h rename to arch/arm/mach-lpc13xx/defines/core_cm3.h diff --git a/arch/arm/mach-lpc_m3/defines/lpc13xx.h b/arch/arm/mach-lpc13xx/defines/lpc13xx-arm.h similarity index 97% rename from arch/arm/mach-lpc_m3/defines/lpc13xx.h rename to arch/arm/mach-lpc13xx/defines/lpc13xx-arm.h index 4d71c34..59bec06 100644 --- a/arch/arm/mach-lpc_m3/defines/lpc13xx.h +++ b/arch/arm/mach-lpc13xx/defines/lpc13xx-arm.h @@ -1,493 +1,493 @@ -/**************************************************************************//** - * @file LPC13xx.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for - * NXP LPC13xx Device Series - * @version V1.01 - * @date 19. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __LPC13xx_H__ -#define __LPC13xx_H__ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ - -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** LPC13xx Specific Interrupt Numbers *******************************************************/ - WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ - WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ - WAKEUP2_IRQn = 2, - WAKEUP3_IRQn = 3, - WAKEUP4_IRQn = 4, - WAKEUP5_IRQn = 5, - WAKEUP6_IRQn = 6, - WAKEUP7_IRQn = 7, - WAKEUP8_IRQn = 8, - WAKEUP9_IRQn = 9, - WAKEUP10_IRQn = 10, - WAKEUP11_IRQn = 11, - WAKEUP12_IRQn = 12, - WAKEUP13_IRQn = 13, - WAKEUP14_IRQn = 14, - WAKEUP15_IRQn = 15, - WAKEUP16_IRQn = 16, - WAKEUP17_IRQn = 17, - WAKEUP18_IRQn = 18, - WAKEUP19_IRQn = 19, - WAKEUP20_IRQn = 20, - WAKEUP21_IRQn = 21, - WAKEUP22_IRQn = 22, - WAKEUP23_IRQn = 23, - WAKEUP24_IRQn = 24, - WAKEUP25_IRQn = 25, - WAKEUP26_IRQn = 26, - WAKEUP27_IRQn = 27, - WAKEUP28_IRQn = 28, - WAKEUP29_IRQn = 29, - WAKEUP30_IRQn = 30, - WAKEUP31_IRQn = 31, - WAKEUP32_IRQn = 32, - WAKEUP33_IRQn = 33, - WAKEUP34_IRQn = 34, - WAKEUP35_IRQn = 35, - WAKEUP36_IRQn = 36, - WAKEUP37_IRQn = 37, - WAKEUP38_IRQn = 38, - WAKEUP39_IRQn = 39, - I2C_IRQn = 40, /*!< I2C Interrupt */ - TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ - TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ - TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ - TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ - SSP_IRQn = 45, /*!< SSP Interrupt */ - UART_IRQn = 46, /*!< UART Interrupt */ - USB_IRQn = 47, /*!< USB Regular Interrupt */ - USB_FIQn = 48, /*!< USB Fast Interrupt */ - ADC_IRQn = 49, /*!< A/D Converter Interrupt */ - WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ - BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ - EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ - EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ - EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ - EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ -} IRQn_Type; - - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M3 Processor and Core Peripherals */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - - -#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ -//#include "system_LPC13xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SYSCON) --------------------------------------*/ -typedef struct -{ - __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */ - __IO uint32_t PRESETCTRL; - __IO uint32_t SYSPLLCTRL; /* Sys PLL control */ - __IO uint32_t SYSPLLSTAT; - __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ - __IO uint32_t USBPLLSTAT; - uint32_t RESERVED0[2]; - - __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */ - __IO uint32_t WDTOSCCTRL; - __IO uint32_t IRCCTRL; - uint32_t RESERVED1[1]; - __IO uint32_t SYSRESSTAT; /* Offset 0x30 */ - uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */ - __IO uint32_t SYSPLLCLKUEN; - __IO uint32_t USBPLLCLKSEL; - __IO uint32_t USBPLLCLKUEN; - uint32_t RESERVED3[8]; - - __IO uint32_t MAINCLKSEL; /* Offset 0x70 */ - __IO uint32_t MAINCLKUEN; - __IO uint32_t SYSAHBCLKDIV; - uint32_t RESERVED4[1]; - - __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */ - uint32_t RESERVED5[4]; - __IO uint32_t SSPCLKDIV; - __IO uint32_t UARTCLKDIV; - uint32_t RESERVED6[4]; - __IO uint32_t TRACECLKDIV; - - __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ - uint32_t RESERVED7[3]; - - __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ - __IO uint32_t USBCLKUEN; - __IO uint32_t USBCLKDIV; - uint32_t RESERVED8[1]; - __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */ - __IO uint32_t WDTCLKUEN; - __IO uint32_t WDTCLKDIV; - uint32_t RESERVED9[1]; - __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */ - __IO uint32_t CLKOUTUEN; - __IO uint32_t CLKOUTDIV; - uint32_t RESERVED10[5]; - - __IO uint32_t PIOPORCAP0; /* Offset 0x100 */ - __IO uint32_t PIOPORCAP1; - uint32_t RESERVED11[18]; - - __IO uint32_t BODCTRL; /* Offset 0x150 */ - uint32_t RESERVED12[1]; - __IO uint32_t SYSTCKCAL; - uint32_t RESERVED13[41]; - - __IO uint32_t STARTAPRP0; /* Offset 0x200 */ - __IO uint32_t STARTERP0; - __IO uint32_t STARTRSRP0CLR; - __IO uint32_t STARTSRP0; - __IO uint32_t STARTAPRP1; - __IO uint32_t STARTERP1; - __IO uint32_t STARTRSRP1CLR; - __IO uint32_t STARTSRP1; - uint32_t RESERVED14[4]; - - __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */ - __IO uint32_t PDAWAKECFG; - __IO uint32_t PDRUNCFG; - uint32_t RESERVED15[110]; - __I uint32_t DEVICE_ID; -} LPC_SYSCON_TypeDef; - - -/*------------- Pin Connect Block (IOCON) --------------------------------*/ -typedef struct -{ - __IO uint32_t PIO2_6; - uint32_t RESERVED0[1]; - __IO uint32_t PIO2_0; - __IO uint32_t RESET_PIO0_0; - __IO uint32_t PIO0_1; - __IO uint32_t PIO1_8; - uint32_t RESERVED1[1]; - __IO uint32_t PIO0_2; - - __IO uint32_t PIO2_7; - __IO uint32_t PIO2_8; - __IO uint32_t PIO2_1; - __IO uint32_t PIO0_3; - __IO uint32_t PIO0_4; - __IO uint32_t PIO0_5; - __IO uint32_t PIO1_9; - __IO uint32_t PIO3_4; - - __IO uint32_t PIO2_4; - __IO uint32_t PIO2_5; - __IO uint32_t PIO3_5; - __IO uint32_t PIO0_6; - __IO uint32_t PIO0_7; - __IO uint32_t PIO2_9; - __IO uint32_t PIO2_10; - __IO uint32_t PIO2_2; - - __IO uint32_t PIO0_8; - __IO uint32_t PIO0_9; - __IO uint32_t JTAG_TCK_PIO0_10; - __IO uint32_t PIO1_10; - __IO uint32_t PIO2_11; - __IO uint32_t JTAG_TDI_PIO0_11; - __IO uint32_t JTAG_TMS_PIO1_0; - __IO uint32_t JTAG_TDO_PIO1_1; - - __IO uint32_t JTAG_nTRST_PIO1_2; - __IO uint32_t PIO3_0; - __IO uint32_t PIO3_1; - __IO uint32_t PIO2_3; - __IO uint32_t ARM_SWDIO_PIO1_3; - __IO uint32_t PIO1_4; - __IO uint32_t PIO1_11; - __IO uint32_t PIO3_2; - - __IO uint32_t PIO1_5; - __IO uint32_t PIO1_6; - __IO uint32_t PIO1_7; - __IO uint32_t PIO3_3; - __IO uint32_t SCKLOC; /* For HB1 only, new feature */ -} LPC_IOCON_TypeDef; - - -/*------------- Power Management Unit (PMU) --------------------------*/ -typedef struct -{ - __IO uint32_t PCON; - __IO uint32_t GPREG0; - __IO uint32_t GPREG1; - __IO uint32_t GPREG2; - __IO uint32_t GPREG3; - __IO uint32_t GPREG4; -} LPC_PMU_TypeDef; - - -/*------------- General Purpose Input/Output (GPIO) --------------------------*/ -typedef struct -{ - union { - __IO uint32_t MASKED_ACCESS[4096]; - struct { - uint32_t RESERVED0[4095]; - __IO uint32_t DATA; - }; - }; - uint32_t RESERVED1[4096]; - __IO uint32_t DIR; - __IO uint32_t IS; - __IO uint32_t IBE; - __IO uint32_t IEV; - __IO uint32_t IE; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t IC; -} LPC_GPIO_TypeDef; - - -/*------------- Timer (TMR) --------------------------------------------------*/ -typedef struct -{ - __IO uint32_t IR; - __IO uint32_t TCR; - __IO uint32_t TC; - __IO uint32_t PR; - __IO uint32_t PC; - __IO uint32_t MCR; - __IO uint32_t MR0; - __IO uint32_t MR1; - __IO uint32_t MR2; - __IO uint32_t MR3; - __IO uint32_t CCR; - __I uint32_t CR0; - uint32_t RESERVED1[3]; - __IO uint32_t EMR; - uint32_t RESERVED2[12]; - __IO uint32_t CTCR; - __IO uint32_t PWMC; -} LPC_TMR_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ -typedef struct -{ - union { - __I uint32_t RBR; - __O uint32_t THR; - __IO uint32_t DLL; - }; - union { - __IO uint32_t DLM; - __IO uint32_t IER; - }; - union { - __I uint32_t IIR; - __O uint32_t FCR; - }; - __IO uint32_t LCR; - __IO uint32_t MCR; - __I uint32_t LSR; - __I uint32_t MSR; - __IO uint32_t SCR; - __IO uint32_t ACR; - __IO uint32_t ICR; - __IO uint32_t FDR; - uint32_t RESERVED0; - __IO uint32_t TER; - uint32_t RESERVED1[6]; - __IO uint32_t RS485CTRL; - __IO uint32_t ADRMATCH; - __IO uint32_t RS485DLY; - __I uint32_t FIFOLVL; -} LPC_UART_TypeDef; - -/*------------- Synchronous Serial Communication (SSP) -----------------------*/ -typedef struct -{ - __IO uint32_t CR0; - __IO uint32_t CR1; - __IO uint32_t DR; - __I uint32_t SR; - __IO uint32_t CPSR; - __IO uint32_t IMSC; - __IO uint32_t RIS; - __IO uint32_t MIS; - __IO uint32_t ICR; -} LPC_SSP_TypeDef; - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -typedef struct -{ - __IO uint32_t CONSET; - __I uint32_t STAT; - __IO uint32_t DAT; - __IO uint32_t ADR0; - __IO uint32_t SCLH; - __IO uint32_t SCLL; - __O uint32_t CONCLR; - __IO uint32_t MMCTRL; - __IO uint32_t ADR1; - __IO uint32_t ADR2; - __IO uint32_t ADR3; - __I uint32_t DATA_BUFFER; - __IO uint32_t MASK0; - __IO uint32_t MASK1; - __IO uint32_t MASK2; - __IO uint32_t MASK3; -} LPC_I2C_TypeDef; - -/*------------- Watchdog Timer (WDT) -----------------------------------------*/ -typedef struct -{ - __IO uint32_t MOD; - __IO uint32_t TC; - __O uint32_t FEED; - __I uint32_t TV; -} LPC_WDT_TypeDef; - -/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t GDR; - uint32_t RESERVED0; - __IO uint32_t INTEN; - __I uint32_t DR0; - __I uint32_t DR1; - __I uint32_t DR2; - __I uint32_t DR3; - __I uint32_t DR4; - __I uint32_t DR5; - __I uint32_t DR6; - __I uint32_t DR7; - __I uint32_t STAT; -} LPC_ADC_TypeDef; - - -/*------------- Universal Serial Bus (USB) -----------------------------------*/ -typedef struct -{ - __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ - __IO uint32_t DevIntEn; - __O uint32_t DevIntClr; - __O uint32_t DevIntSet; - - __O uint32_t CmdCode; /* USB Device SIE Command Registers */ - __I uint32_t CmdData; - - __I uint32_t RxData; /* USB Device Transfer Registers */ - __O uint32_t TxData; - __I uint32_t RxPLen; - __O uint32_t TxPLen; - __IO uint32_t Ctrl; - __O uint32_t DevFIQSel; -} LPC_USB_TypeDef; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_AHB_BASE (0x50000000UL) - -/* APB0 peripherals */ -#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) -#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) -#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) -#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) -#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) -#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) - -/* AHB peripherals */ -#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) -#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) -#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) -#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) -#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) -#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) -#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) -#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) -#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) -#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) -#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) -#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) -#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) -#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) -#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) -#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) -#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) - -#endif // __LPC13xx_H__ +/**************************************************************************//** + * @file LPC13xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC13xx Device Series + * @version V1.01 + * @date 19. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC13xx_H__ +#define __LPC13xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC13xx Specific Interrupt Numbers *******************************************************/ + WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ + WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ + WAKEUP2_IRQn = 2, + WAKEUP3_IRQn = 3, + WAKEUP4_IRQn = 4, + WAKEUP5_IRQn = 5, + WAKEUP6_IRQn = 6, + WAKEUP7_IRQn = 7, + WAKEUP8_IRQn = 8, + WAKEUP9_IRQn = 9, + WAKEUP10_IRQn = 10, + WAKEUP11_IRQn = 11, + WAKEUP12_IRQn = 12, + WAKEUP13_IRQn = 13, + WAKEUP14_IRQn = 14, + WAKEUP15_IRQn = 15, + WAKEUP16_IRQn = 16, + WAKEUP17_IRQn = 17, + WAKEUP18_IRQn = 18, + WAKEUP19_IRQn = 19, + WAKEUP20_IRQn = 20, + WAKEUP21_IRQn = 21, + WAKEUP22_IRQn = 22, + WAKEUP23_IRQn = 23, + WAKEUP24_IRQn = 24, + WAKEUP25_IRQn = 25, + WAKEUP26_IRQn = 26, + WAKEUP27_IRQn = 27, + WAKEUP28_IRQn = 28, + WAKEUP29_IRQn = 29, + WAKEUP30_IRQn = 30, + WAKEUP31_IRQn = 31, + WAKEUP32_IRQn = 32, + WAKEUP33_IRQn = 33, + WAKEUP34_IRQn = 34, + WAKEUP35_IRQn = 35, + WAKEUP36_IRQn = 36, + WAKEUP37_IRQn = 37, + WAKEUP38_IRQn = 38, + WAKEUP39_IRQn = 39, + I2C_IRQn = 40, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ + SSP_IRQn = 45, /*!< SSP Interrupt */ + UART_IRQn = 46, /*!< UART Interrupt */ + USB_IRQn = 47, /*!< USB Regular Interrupt */ + USB_FIQn = 48, /*!< USB Fast Interrupt */ + ADC_IRQn = 49, /*!< A/D Converter Interrupt */ + WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ + EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ + EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ + EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ + EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +//#include "system_LPC13xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */ + __IO uint32_t PRESETCTRL; + __IO uint32_t SYSPLLCTRL; /* Sys PLL control */ + __IO uint32_t SYSPLLSTAT; + __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ + __IO uint32_t USBPLLSTAT; + uint32_t RESERVED0[2]; + + __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */ + __IO uint32_t WDTOSCCTRL; + __IO uint32_t IRCCTRL; + uint32_t RESERVED1[1]; + __IO uint32_t SYSRESSTAT; /* Offset 0x30 */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */ + __IO uint32_t SYSPLLCLKUEN; + __IO uint32_t USBPLLCLKSEL; + __IO uint32_t USBPLLCLKUEN; + uint32_t RESERVED3[8]; + + __IO uint32_t MAINCLKSEL; /* Offset 0x70 */ + __IO uint32_t MAINCLKUEN; + __IO uint32_t SYSAHBCLKDIV; + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */ + uint32_t RESERVED5[4]; + __IO uint32_t SSPCLKDIV; + __IO uint32_t UARTCLKDIV; + uint32_t RESERVED6[4]; + __IO uint32_t TRACECLKDIV; + + __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ + uint32_t RESERVED7[3]; + + __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ + __IO uint32_t USBCLKUEN; + __IO uint32_t USBCLKDIV; + uint32_t RESERVED8[1]; + __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */ + __IO uint32_t WDTCLKUEN; + __IO uint32_t WDTCLKDIV; + uint32_t RESERVED9[1]; + __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */ + __IO uint32_t CLKOUTUEN; + __IO uint32_t CLKOUTDIV; + uint32_t RESERVED10[5]; + + __IO uint32_t PIOPORCAP0; /* Offset 0x100 */ + __IO uint32_t PIOPORCAP1; + uint32_t RESERVED11[18]; + + __IO uint32_t BODCTRL; /* Offset 0x150 */ + uint32_t RESERVED12[1]; + __IO uint32_t SYSTCKCAL; + uint32_t RESERVED13[41]; + + __IO uint32_t STARTAPRP0; /* Offset 0x200 */ + __IO uint32_t STARTERP0; + __IO uint32_t STARTRSRP0CLR; + __IO uint32_t STARTSRP0; + __IO uint32_t STARTAPRP1; + __IO uint32_t STARTERP1; + __IO uint32_t STARTRSRP1CLR; + __IO uint32_t STARTSRP1; + uint32_t RESERVED14[4]; + + __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */ + __IO uint32_t PDAWAKECFG; + __IO uint32_t PDRUNCFG; + uint32_t RESERVED15[110]; + __I uint32_t DEVICE_ID; +} LPC_SYSCON_TypeDef; + + +/*------------- Pin Connect Block (IOCON) --------------------------------*/ +typedef struct +{ + __IO uint32_t PIO2_6; + uint32_t RESERVED0[1]; + __IO uint32_t PIO2_0; + __IO uint32_t RESET_PIO0_0; + __IO uint32_t PIO0_1; + __IO uint32_t PIO1_8; + uint32_t RESERVED1[1]; + __IO uint32_t PIO0_2; + + __IO uint32_t PIO2_7; + __IO uint32_t PIO2_8; + __IO uint32_t PIO2_1; + __IO uint32_t PIO0_3; + __IO uint32_t PIO0_4; + __IO uint32_t PIO0_5; + __IO uint32_t PIO1_9; + __IO uint32_t PIO3_4; + + __IO uint32_t PIO2_4; + __IO uint32_t PIO2_5; + __IO uint32_t PIO3_5; + __IO uint32_t PIO0_6; + __IO uint32_t PIO0_7; + __IO uint32_t PIO2_9; + __IO uint32_t PIO2_10; + __IO uint32_t PIO2_2; + + __IO uint32_t PIO0_8; + __IO uint32_t PIO0_9; + __IO uint32_t JTAG_TCK_PIO0_10; + __IO uint32_t PIO1_10; + __IO uint32_t PIO2_11; + __IO uint32_t JTAG_TDI_PIO0_11; + __IO uint32_t JTAG_TMS_PIO1_0; + __IO uint32_t JTAG_TDO_PIO1_1; + + __IO uint32_t JTAG_nTRST_PIO1_2; + __IO uint32_t PIO3_0; + __IO uint32_t PIO3_1; + __IO uint32_t PIO2_3; + __IO uint32_t ARM_SWDIO_PIO1_3; + __IO uint32_t PIO1_4; + __IO uint32_t PIO1_11; + __IO uint32_t PIO3_2; + + __IO uint32_t PIO1_5; + __IO uint32_t PIO1_6; + __IO uint32_t PIO1_7; + __IO uint32_t PIO3_3; + __IO uint32_t SCKLOC; /* For HB1 only, new feature */ +} LPC_IOCON_TypeDef; + + +/*------------- Power Management Unit (PMU) --------------------------*/ +typedef struct +{ + __IO uint32_t PCON; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; +} LPC_PMU_TypeDef; + + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t MASKED_ACCESS[4096]; + struct { + uint32_t RESERVED0[4095]; + __IO uint32_t DATA; + }; + }; + uint32_t RESERVED1[4096]; + __IO uint32_t DIR; + __IO uint32_t IS; + __IO uint32_t IBE; + __IO uint32_t IEV; + __IO uint32_t IE; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t IC; +} LPC_GPIO_TypeDef; + + +/*------------- Timer (TMR) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + uint32_t RESERVED1[3]; + __IO uint32_t EMR; + uint32_t RESERVED2[12]; + __IO uint32_t CTCR; + __IO uint32_t PWMC; +} LPC_TMR_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint32_t RBR; + __O uint32_t THR; + __IO uint32_t DLL; + }; + union { + __IO uint32_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint32_t FCR; + }; + __IO uint32_t LCR; + __IO uint32_t MCR; + __I uint32_t LSR; + __I uint32_t MSR; + __IO uint32_t SCR; + __IO uint32_t ACR; + __IO uint32_t ICR; + __IO uint32_t FDR; + uint32_t RESERVED0; + __IO uint32_t TER; + uint32_t RESERVED1[6]; + __IO uint32_t RS485CTRL; + __IO uint32_t ADRMATCH; + __IO uint32_t RS485DLY; + __I uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t CONSET; + __I uint32_t STAT; + __IO uint32_t DAT; + __IO uint32_t ADR0; + __IO uint32_t SCLH; + __IO uint32_t SCLL; + __O uint32_t CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t ADR1; + __IO uint32_t ADR2; + __IO uint32_t ADR3; + __I uint32_t DATA_BUFFER; + __IO uint32_t MASK0; + __IO uint32_t MASK1; + __IO uint32_t MASK2; + __IO uint32_t MASK3; +} LPC_I2C_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t MOD; + __IO uint32_t TC; + __O uint32_t FEED; + __I uint32_t TV; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t GDR; + uint32_t RESERVED0; + __IO uint32_t INTEN; + __I uint32_t DR0; + __I uint32_t DR1; + __I uint32_t DR2; + __I uint32_t DR3; + __I uint32_t DR4; + __I uint32_t DR5; + __I uint32_t DR6; + __I uint32_t DR7; + __I uint32_t STAT; +} LPC_ADC_TypeDef; + + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t DevIntEn; + __O uint32_t DevIntClr; + __O uint32_t DevIntSet; + + __O uint32_t CmdCode; /* USB Device SIE Command Registers */ + __I uint32_t CmdData; + + __I uint32_t RxData; /* USB Device Transfer Registers */ + __O uint32_t TxData; + __I uint32_t RxPLen; + __O uint32_t TxPLen; + __IO uint32_t Ctrl; + __O uint32_t DevFIQSel; +} LPC_USB_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) +#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) + +/* AHB peripherals */ +#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) +#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) +#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) +#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) +#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) +#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) +#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) + +#endif // __LPC13xx_H__ diff --git a/arch/arm/mach-lpc13xx/defines/lpc13xx.h b/arch/arm/mach-lpc13xx/defines/lpc13xx.h new file mode 100644 index 0000000..fa5cdf7 --- /dev/null +++ b/arch/arm/mach-lpc13xx/defines/lpc13xx.h @@ -0,0 +1,81 @@ +#ifndef __LPC13xx_H +#define __LPC13xx_H + +#include "lpc13xx-arm.h" + +/* UART reg aliases */ + +/* match with LPC2xxx registers */ +#define U0RBR (LPC_UART->RBR) +#define U0THR (LPC_UART->THR) +#define U0DLL (LPC_UART->DLL) +#define U0DLM (LPC_UART->DLM) +#define U0IER (LPC_UART->IER) +#define U0IIR (LPC_UART->IIR) +#define U0FCR (LPC_UART->FCR) +#define U0LCR (LPC_UART->LCR) +#define U0MCR (LPC_UART->MCR) +#define U0LSR (LPC_UART->LSR) +#define U0MSR (LPC_UART->MSR) +#define U0SCR (LPC_UART->SCR) +#define U0ACR (LPC_UART->ACR) +#define U0ICR (LPC_UART->ICR) +#define U0FDR (LPC_UART->FDR) +#define U0TER (LPC_UART->TER) +/* regs newly introduced in 13xx series */ +#define U0RS485CTRL (LPC_UART->RS485CTRL) +#define U0ADRMATCH (LPC_UART->ADRMATCH) +#define U0RS485DLY (LPC_UART->RS485DLY) +#define U0FIFOLVL (LPC_UART->FIFOLVL) + +/* I/O pin connect block */ + +#define IOCON_RESET_PIO0_0 (LPC_IOCON->RESET_PIO0_0) +#define IOCON_PIO0_1 (LPC_IOCON->PIO0_1) +#define IOCON_PIO0_2 (LPC_IOCON->PIO0_2) +#define IOCON_PIO0_3 (LPC_IOCON->PIO0_3) +#define IOCON_PIO0_4 (LPC_IOCON->PIO0_4) +#define IOCON_PIO0_5 (LPC_IOCON->PIO0_5) +#define IOCON_PIO0_6 (LPC_IOCON->PIO0_6) +#define IOCON_PIO0_7 (LPC_IOCON->PIO0_7) +#define IOCON_PIO0_8 (LPC_IOCON->PIO0_8) +#define IOCON_PIO0_9 (LPC_IOCON->PIO0_9) +#define IOCON_JTAG_TCK_PIO0_10 (LPC_IOCON->JTAG_TCK_PIO0_10) +#define IOCON_JTAG_TDI_PIO0_11 (LPC_IOCON->JTAG_TDI_PIO0_11) + +#define IOCON_JTAG_TMS_PIO1_0 (LPC_IOCON->JTAG_TMS_PIO1_0) +#define IOCON_JTAG_TDO_PIO1_1 (LPC_IOCON->JTAG_TDO_PIO1_1) +#define IOCON_JTAG_nTRST_PIO1_2 (LPC_IOCON->JTAG_nTRST_PIO1_2) +#define IOCON_ARM_SWDIO_PIO1_3 (LPC_IOCON->ARM_SWDIO_PIO1_3) +#define IOCON_PIO1_4 (LPC_IOCON->PIO1_4) +#define IOCON_PIO1_5 (LPC_IOCON->PIO1_5) +#define IOCON_PIO1_6 (LPC_IOCON->PIO1_6) +#define IOCON_PIO1_7 (LPC_IOCON->PIO1_7) +#define IOCON_PIO1_8 (LPC_IOCON->PIO1_8) +#define IOCON_PIO1_9 (LPC_IOCON->PIO1_9) +#define IOCON_PIO1_10 (LPC_IOCON->PIO1_10) +#define IOCON_PIO1_11 (LPC_IOCON->PIO1_11) + +#define IOCON_PIO2_0 (LPC_IOCON->PIO2_0) +#define IOCON_PIO2_1 (LPC_IOCON->PIO2_1) +#define IOCON_PIO2_10 (LPC_IOCON->PIO2_10) +#define IOCON_PIO2_11 (LPC_IOCON->PIO2_11) +#define IOCON_PIO2_2 (LPC_IOCON->PIO2_2) +#define IOCON_PIO2_3 (LPC_IOCON->PIO2_3) +#define IOCON_PIO2_4 (LPC_IOCON->PIO2_4) +#define IOCON_PIO2_5 (LPC_IOCON->PIO2_5) +#define IOCON_PIO2_6 (LPC_IOCON->PIO2_6) +#define IOCON_PIO2_7 (LPC_IOCON->PIO2_7) +#define IOCON_PIO2_8 (LPC_IOCON->PIO2_8) +#define IOCON_PIO2_9 (LPC_IOCON->PIO2_9) + +#define IOCON_PIO3_0 (LPC_IOCON->PIO3_0) +#define IOCON_PIO3_1 (LPC_IOCON->PIO3_1) +#define IOCON_PIO3_2 (LPC_IOCON->PIO3_2) +#define IOCON_PIO3_3 (LPC_IOCON->PIO3_3) +#define IOCON_PIO3_4 (LPC_IOCON->PIO3_4) +#define IOCON_PIO3_5 (LPC_IOCON->PIO3_5) + +#define IOCON_SCKLOC (LPC_IOCON->SCKLOC) + +#endif /* __LPC13xx_H */ diff --git a/arch/arm/mach-lpc13xx/defines/lpc2xxx.h b/arch/arm/mach-lpc13xx/defines/lpc2xxx.h new file mode 100644 index 0000000..55c96bf --- /dev/null +++ b/arch/arm/mach-lpc13xx/defines/lpc2xxx.h @@ -0,0 +1,2 @@ +/* partial register compatibility with LPC2xxx series */ +#include "lpc13xx.h" diff --git a/arch/arm/mach-lpc_m3/libs/Makefile b/arch/arm/mach-lpc13xx/libs/Makefile similarity index 100% rename from arch/arm/mach-lpc_m3/libs/Makefile rename to arch/arm/mach-lpc13xx/libs/Makefile diff --git a/arch/arm/mach-lpc_m3/libs/Makefile.omk b/arch/arm/mach-lpc13xx/libs/Makefile.omk similarity index 100% rename from arch/arm/mach-lpc_m3/libs/Makefile.omk rename to arch/arm/mach-lpc13xx/libs/Makefile.omk diff --git a/arch/arm/mach-lpc_m3/libs/boot/Makefile b/arch/arm/mach-lpc13xx/libs/boot/Makefile similarity index 100% rename from arch/arm/mach-lpc_m3/libs/boot/Makefile rename to arch/arm/mach-lpc13xx/libs/boot/Makefile diff --git a/arch/arm/mach-lpc_m3/libs/boot/Makefile.omk b/arch/arm/mach-lpc13xx/libs/boot/Makefile.omk similarity index 100% rename from arch/arm/mach-lpc_m3/libs/boot/Makefile.omk rename to arch/arm/mach-lpc13xx/libs/boot/Makefile.omk diff --git a/arch/arm/mach-lpc_m3/libs/boot/crt0_13xx.c b/arch/arm/mach-lpc13xx/libs/boot/crt0_13xx.c similarity index 97% rename from arch/arm/mach-lpc_m3/libs/boot/crt0_13xx.c rename to arch/arm/mach-lpc13xx/libs/boot/crt0_13xx.c index e1df13b..2308fcd 100644 --- a/arch/arm/mach-lpc_m3/libs/boot/crt0_13xx.c +++ b/arch/arm/mach-lpc13xx/libs/boot/crt0_13xx.c @@ -99,7 +99,7 @@ __attribute__((section(".ivec"))) WAKEUP_IRQHandler, /* 20 4 Wake-up on pin PIO0_4 */ WAKEUP_IRQHandler, /* 21 5 Wake-up on pin PIO0_5 */ WAKEUP_IRQHandler, /* 22 6 Wake-up on pin PIO0_6 */ - WAKEUP_IRQHandler, /* 23 7 Wake-up on pin PIO0_7 */ + WAKEUP_IRQHandler, /* 23 7 Wake-up on pin PIO0_7 */ WAKEUP_IRQHandler, /* 24 8 Wake-up on pin PIO0_8 */ WAKEUP_IRQHandler, /* 25 9 Wake-up on pin PIO0_9 */ WAKEUP_IRQHandler, /* 26 10 Wake-up on pin PIO0_10 */ @@ -129,7 +129,7 @@ __attribute__((section(".ivec"))) WAKEUP_IRQHandler, /* 50 34 Wake-up on pin PIO2_10 */ WAKEUP_IRQHandler, /* 51 35 Wake-up on pin PIO2_11 */ WAKEUP_IRQHandler, /* 52 36 Wake-up on pin PIO3_0 */ - WAKEUP_IRQHandler, /* 53 37 Wake-up on pin PIO3_1 */ + WAKEUP_IRQHandler, /* 53 37 Wake-up on pin PIO3_1 */ WAKEUP_IRQHandler, /* 54 38 Wake-up on pin PIO3_2 */ WAKEUP_IRQHandler, /* 55 39 Wake-up on pin PIO3_3 */ I2C_IRQHandler, /* 56 40 I2C0 SI (state change) */ @@ -142,13 +142,13 @@ __attribute__((section(".ivec"))) USB_IRQHandler, /* 63 47 USB IRQ low priority */ USB_FIQHandler, /* 64 48 USB FIQ high priority */ ADC_IRQHandler, /* 65 49 ADC end of conversion */ - WDT_IRQHandler, /* 66 50 Watchdog interrupt (WDINT) */ - BOD_IRQHandler, /* 67 51 BOD Brown-out detect */ + WDT_IRQHandler, /* 66 50 Watchdog interrupt (WDINT) */ + BOD_IRQHandler, /* 67 51 BOD Brown-out detect */ FMC_IRQHandler, /* 68 52 Reserved also marked as IP2111 Flash Memory */ - PIOINT3_IRQHandler, /* 69 53 PIO_3 GPIO interrupt status of port 3 */ - PIOINT2_IRQHandler, /* 70 54 PIO_2 GPIO interrupt status of port 2 */ - PIOINT1_IRQHandler, /* 71 55 PIO_1 GPIO interrupt status of port 1 */ - PIOINT0_IRQHandler, /* 72 56 PIO_0 GPIO interrupt status of port 0 */ + PIOINT3_IRQHandler, /* 69 53 PIO_3 GPIO interrupt status of port 3 */ + PIOINT2_IRQHandler, /* 70 54 PIO_2 GPIO interrupt status of port 2 */ + PIOINT1_IRQHandler, /* 71 55 PIO_1 GPIO interrupt status of port 1 */ + PIOINT0_IRQHandler, /* 72 56 PIO_0 GPIO interrupt status of port 0 */ }; /* @@ -177,7 +177,7 @@ void _start() { /* * remap IRQ vector or not, depending on their RAM/ROM location */ - LPC_SYSCON->SYSMEMREMAP = 1 + (&_vectors == (uint32_t*)0x0); + LPC_SYSCON->SYSMEMREMAP = 1 + (&_vectors == (void*)0x0); /* Call init functions in .init_array section (only if __libc_init_array exists) */ if (__libc_init_array) diff --git a/arch/arm/mach-lpc_m3/libs/boot/initarray.c b/arch/arm/mach-lpc13xx/libs/boot/initarray.c similarity index 100% rename from arch/arm/mach-lpc_m3/libs/boot/initarray.c rename to arch/arm/mach-lpc13xx/libs/boot/initarray.c diff --git a/arch/arm/mach-lpc_m3/libs/ldscripts/Makefile b/arch/arm/mach-lpc13xx/libs/ldscripts/Makefile similarity index 100% rename from arch/arm/mach-lpc_m3/libs/ldscripts/Makefile rename to arch/arm/mach-lpc13xx/libs/ldscripts/Makefile diff --git a/arch/arm/mach-lpc_m3/libs/ldscripts/Makefile.omk b/arch/arm/mach-lpc13xx/libs/ldscripts/Makefile.omk similarity index 100% rename from arch/arm/mach-lpc_m3/libs/ldscripts/Makefile.omk rename to arch/arm/mach-lpc13xx/libs/ldscripts/Makefile.omk diff --git a/arch/arm/mach-lpc13xx/libs/ldscripts/lpc1311.ld-flash b/arch/arm/mach-lpc13xx/libs/ldscripts/lpc1311.ld-flash new file mode 100644 index 0000000..a857dc1 --- /dev/null +++ b/arch/arm/mach-lpc13xx/libs/ldscripts/lpc1311.ld-flash @@ -0,0 +1,19 @@ +/* + * LPC1311 internal FLASH (8KB FLASH + 4KB SRAM) + */ + +STARTUP(crt0_13xx.o) +INCLUDE board.ld /* Allow to INPUT board specific files */ + +ENTRY(_start) +STACK_SIZE = 0x400; + +/* memory definitions */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000 + RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x01000 +} + +/* include section definitions */ +INCLUDE lpc13xx-flash.ld diff --git a/arch/arm/mach-lpc_m3/libs/ldscripts/lpc1311.ld-ram b/arch/arm/mach-lpc13xx/libs/ldscripts/lpc1311.ld-ram similarity index 100% rename from arch/arm/mach-lpc_m3/libs/ldscripts/lpc1311.ld-ram rename to arch/arm/mach-lpc13xx/libs/ldscripts/lpc1311.ld-ram diff --git a/arch/arm/mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld b/arch/arm/mach-lpc13xx/libs/ldscripts/lpc13xx-flash.ld similarity index 91% copy from arch/arm/mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld copy to arch/arm/mach-lpc13xx/libs/ldscripts/lpc13xx-flash.ld index 3b9eadc..b268ec7 100644 --- a/arch/arm/mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld +++ b/arch/arm/mach-lpc13xx/libs/ldscripts/lpc13xx-flash.ld @@ -1,5 +1,7 @@ /*** - * LPC13xx internal RAM loadable by Philips ISP serial loader + * LPC13xx internal FLASH loadable by ISP + * uses internal FLASH and whole RAM at runtime + * * by Marek Peca <mp@duch.cz> 2009/09, 2010/06 ***/ @@ -12,21 +14,25 @@ SECTIONS .ivec : { *(.ivec) /* interrupt entry points */ - } > RAM_IVEC + } > FLASH /* first section is .text which is used for code */ .text : { *crt0_13xx.o (.text) /* Startup code */ *(.text) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) *(.glue_7) *(.glue_7t) . = ALIGN(4); _etext = .; - } > RAM_LOAD + } > FLASH + .rodata : + { + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + . = ALIGN(4); + } > FLASH /* .init_array - pointers to functions called before main */ PROVIDE(__init_array_start = .); @@ -34,22 +40,22 @@ SECTIONS { *(.init_array) . = ALIGN(4); - } > RAM_LOAD = 0 + } > FLASH = 0 PROVIDE (__init_array_end = .); /* .data section which is used for initialized data */ + _datainit = LOADADDR(.data); .data : { _data = .; - _datainit = .; *(.data) SORT(CONSTRUCTORS) . = ALIGN(4); _edata = .; - } > RAM_LOAD + } > RAM AT> FLASH /* .bss section which is used for uninitialized data */ - .bss _edata (NOLOAD) : + .bss (NOLOAD) : { __bss_start = .; __bss_start__ = .; diff --git a/arch/arm/mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld b/arch/arm/mach-lpc13xx/libs/ldscripts/lpc13xx-ram.ld similarity index 100% rename from arch/arm/mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld rename to arch/arm/mach-lpc13xx/libs/ldscripts/lpc13xx-ram.ld diff --git a/arch/arm/mach-lpc23xx/libs/uart_zen b/arch/arm/mach-lpc13xx/libs/uart_zen similarity index 100% copy from arch/arm/mach-lpc23xx/libs/uart_zen copy to arch/arm/mach-lpc13xx/libs/uart_zen diff --git a/arch/arm/mach-lpc13xx/tools/lpcchksum/lpcchksum.sh b/arch/arm/mach-lpc13xx/tools/lpcchksum/lpcchksum.sh new file mode 100755 index 0000000..353af27 --- /dev/null +++ b/arch/arm/mach-lpc13xx/tools/lpcchksum/lpcchksum.sh @@ -0,0 +1,6 @@ +#!/bin/bash + +cksum=$[($(hexdump -v -n $[7*4] -e '1/4 "0x%08x+"' $1) - 1)^0xffffffff] +( head -c $[7*4] $1; \ + echo -en $(printf '%08x' $cksum | sed 's/.*\(..\)\(..\)\(..\)\(..\)$/\\x\4\\x\3\\x\2\\x\1/'); \ + tail -c +$[8*4] $1 ) diff --git a/arch/arm/mach-lpc21xx/libs/uart_zen/uart_zen.c b/arch/arm/mach-lpc21xx/libs/uart_zen/uart_zen.c index 407550b..13b8602 100644 --- a/arch/arm/mach-lpc21xx/libs/uart_zen/uart_zen.c +++ b/arch/arm/mach-lpc21xx/libs/uart_zen/uart_zen.c @@ -43,11 +43,19 @@ volatile uint8_t err_flag[2] = {0, 0}; //!< UART0 and UART1 error flags volatile uint16_t write_buffer_index[2] = {0, 0}, read_buffer_index[2] = {0, 0}; //!< UART0 and UART1 read and write buffer indexes uint8_t buff[2][UART_BUFF_LEN]; //!< UART0 and UART1 data buffers +#if defined(MACH_LPC21XX) || defined(MACH_LPC23XX) /*! UART0 interrupt handler prototype */ void UART0_irq ( void ) __attribute__ ( ( interrupt ) ); - /*! UART1 interrupt handler prototype */ void UART1_irq ( void ) __attribute__ ( ( interrupt ) ); +#endif + +#if defined(MACH_LPC13XX) +void UART_isr(uint8_t uart_num); +void UART_IRQHandler() { + UART_isr(0); +} +#endif /*! UART interrupt service routine. * \param uart_num unsigned 8-bit int UART number (0 or 1) @@ -65,6 +73,9 @@ void UART_isr ( uint8_t uart_num ) { err_flag[uart_num] |= 0x01; // set the overflow condition bit in the error flag } } +#if defined(MACH_LPC21XX) || defined(MACH_LPC23XX) + VICVectAddr = 0; // int acknowledge +#endif } /*! UART0 Rx interrupt service rutine. @@ -72,7 +83,6 @@ void UART_isr ( uint8_t uart_num ) { */ void UART0_irq ( void ) { UART_isr ( UART0 ); // call UART0 ISR - VICVectAddr = 0; // int acknowledge } /*! UART1 Rx interrupt service rutine. @@ -80,7 +90,6 @@ void UART0_irq ( void ) { */ void UART1_irq ( void ) { UART_isr ( UART1 ); // call UART1 ISR - VICVectAddr = 0; // int acknowledge } /*! UART initialization function. @@ -104,12 +113,14 @@ void UART_init ( uint8_t uart_num, uint32_t baud_rate, uint32_t pclk, unsigned r UART_REG_ADDR ( U0LCR, uart_num ) &= 0x7F; // clear DLAB UART_REG_ADDR ( U0FCR, uart_num ) = 0x01; // enable UART FIFO, interrupt level 1 byte - this might be modified by the user UART_REG_ADDR ( U0IER, uart_num ) = 0x01; // enable Rx interrupt - + +#if defined(MACH_LPC21XX) || defined(MACH_LPC23XX) if ( !uart_num ) ( ( uint32_t * ) &VICVectAddr0 )[rx_isr_vect] = ( uint32_t ) UART0_irq; // if UART0 register UART0 interrupt handler else ( ( uint32_t * ) &VICVectAddr0 )[rx_isr_vect] = ( uint32_t ) UART1_irq; // else register UART1 interrupt handler ( ( uint32_t * ) &VICVectCntl0 )[rx_isr_vect] = 0x20 | ( 6 + uart_num ); // enable IRQ slot, set UART interrupt number VICIntEnable = ( ( uart_num + 1 ) * 0x00000040 ); //enable UART IRQ +#endif } /*! Data read function. diff --git a/board/arm/lpc1311-mini/config.lpc1311-mini b/board/arm/lpc1311-mini/config.lpc1311-mini index fa68d09..c2e1e52 100644 --- a/board/arm/lpc1311-mini/config.lpc1311-mini +++ b/board/arm/lpc1311-mini/config.lpc1311-mini @@ -1,7 +1,7 @@ # -*- makefile -*- ARCH=arm -MACH=lpc_m3 +MACH=lpc13xx BOARD=lpc1311-mini CROSS_COMPILE = arm-elf- @@ -18,12 +18,12 @@ DEBUG ?= -g OPTIMIZE ?= -O2 #LPCISP=~/projects/cf/lpc21isp_v179/lpc21isp -TOLPC_M3=../../../arch/arm/mach-lpc_m3/tools/tolpc/tolpc -m ../../../arch/arm/mach-lpc_m3/tools/tolpc/lpc13xx.so +TOLPC13XX=../../../arch/arm/mach-lpc13xx/tools/tolpc/tolpc -m ../../../arch/arm/mach-lpc13xx/tools/tolpc/lpc13xx.so LPC_BAUD = 115200 LPC_TTY = /dev/ttyUSB0 CPU_SYS_KHZ = 12000 -TOLPC = $(TOLPC_M3) --baud $(LPC_BAUD) --sdev $(LPC_TTY) -q $(CPU_SYS_KHZ) -L -f +TOLPC = $(TOLPC13XX) --baud $(LPC_BAUD) --sdev $(LPC_TTY) -q $(CPU_SYS_KHZ) -L -f LOAD_CMD-ram = $(TOLPC) LOAD_CMD-flash = load() { $(TOLPC) -bin $$1 $(LPC_TTY) $(LPC_BAUD) $(CPU_SYS_KHZ); }; load -- 1.5.5.1 --Pandora3Bndry_12787839561955064162--