On Sat, 19 Jun 2010, Marek Peca wrote:

Nazdar Michale,

nevim, jestli jsem pouzil spravny mail pro patche na sysless, zkousim to poprve.

Priste zkus sysless@pandora.cz :-)

K obsahu: v ulanu jeste neni podpora pro LPC13xx, snazil jsem se jit takovou cestou, abych nehazel klacky pod nohy budouci fuzi, tzn. opisoval jsem, jak se dalo. Zaroven jsem se pridrzel kostry linkerskriptu z LPC23xx, pac mi pripadaj lepsi (initarray opsane od Wentasaha apod.). Zaroven jsem vytvoril arch lpc_m3,

Asi jsi myslel mach lpc_m3, ne?

protoze si zatim nejsem jist, kolik toho maji LPC13xx a LPC17xx spolecneho.

Zdravi Marek diff --git a/app/arm/nazdar1311/Makefile b/app/arm/nazdar1311/Makefile

Zkus priste ten patch vygenerovat pomoci git format-patch a pripadne ho odeslat pomoci git send-email. Usnadnis mi tim praci: 1) budu moct patch okamzite aplikovat (pomoci git am), 2) bude tam diffstat (viz nize), takze jeste nez zacnu studovat ten patch, budu vedet jake soubory jsi pridal/menil/mazal. app/arm/nazdar1311/Makefile | 14 + app/arm/nazdar1311/Makefile.omk | 13 + app/arm/nazdar1311/nazdar.c | 32 + app/arm/nazdar1311/uart.c | 101 ++ app/arm/nazdar1311/uart.h | 47 + arch/arm/mach-lpc_m3/Makefile | 14 + arch/arm/mach-lpc_m3/Makefile.omk | 1 + arch/arm/mach-lpc_m3/defines/Makefile | 14 + arch/arm/mach-lpc_m3/defines/Makefile.omk | 2 + arch/arm/mach-lpc_m3/defines/core_cm3.h | 978 ++++++++++++++++++++ arch/arm/mach-lpc_m3/defines/lpc13xx.h | 493 ++++++++++ arch/arm/mach-lpc_m3/libs/Makefile | 14 + arch/arm/mach-lpc_m3/libs/Makefile.omk | 3 + arch/arm/mach-lpc_m3/libs/boot/Makefile | 14 + arch/arm/mach-lpc_m3/libs/boot/Makefile.omk | 3 + arch/arm/mach-lpc_m3/libs/boot/crt0_13xx.c | 236 +++++ arch/arm/mach-lpc_m3/libs/boot/initarray.c | 1 + arch/arm/mach-lpc_m3/libs/ldscripts/Makefile | 14 + arch/arm/mach-lpc_m3/libs/ldscripts/Makefile.omk | 3 + arch/arm/mach-lpc_m3/libs/ldscripts/lpc1311.ld-ram | 28 + arch/arm/mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld | 104 +++ board/arm/lpc1311-mini/Makefile | 14 + board/arm/lpc1311-mini/Makefile.omk | 6 + board/arm/lpc1311-mini/board.ld | 1 + board/arm/lpc1311-mini/config.lpc1311-mini | 43 + board/arm/lpc1311-mini/system_def.h | 1 + 26 files changed, 2194 insertions(+), 0 deletions(-) Zbytek komentaru posilam nize "inline".

new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/app/arm/nazdar1311/Makefile

Chapu, ze mas rad cestinu, ale ja, kdyz vidim adresar s celkym nazvem v miste, kde se vetsina adresaru jmenuje anglicky, tak mam pocit, ze to je nejakej bordel, kterej tam kdosi zapomnel. Nechces to prejmenovat na hello? Budou ti vdecni i vsichni zahranicni studenti (a jejich vedouci), kteri k nam prijedou na staz a budem je nutit s tim pracovat.

@@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/app/arm/nazdar1311/Makefile.omk b/app/arm/nazdar1311/Makefile.omk new file mode 100644 index 0000000..3da5a76 --- /dev/null +++ b/app/arm/nazdar1311/Makefile.omk @@ -0,0 +1,13 @@ +# -*- makefile -*- + +ifeq ($(MACH),lpc_m3) +bin_PROGRAMS = nazdar1311 + +nazdar1311_SOURCES = nazdar.c uart.c + +link_VARIANTS = ram +else +ifeq ($(RELATIVE_DIR),$(INVOCATION_DIR)) + $(error This works only with LPC13xx machnies!) +endif +endif diff --git a/app/arm/nazdar1311/nazdar.c b/app/arm/nazdar1311/nazdar.c new file mode 100644 index 0000000..8dde369 --- /dev/null +++ b/app/arm/nazdar1311/nazdar.c @@ -0,0 +1,32 @@ +/** tiny lpc1311 uart flood demo, taken from Poppik&Tabak git repo **/ + +#include <stdlib.h> +#include <types.h> +#include <lpc13xx.h> +#include <cpu_def.h> + +#include "uart.h" + +int main() { + LPC_SYSCON->SYSAHBCLKDIV = 1; + LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); //enable clock/power for GPIO

Vyhledove bych se primlouval, aby 1<<6 bylo konstanta v headeru.

+ + uart_simple_init(38400); + + //set PIO1[0] - PIO1[3] to IO + LPC_IOCON->JTAG_TMS_PIO1_0 &= ~0x7; + LPC_IOCON->JTAG_TMS_PIO1_0 |= 0x1; + LPC_IOCON->JTAG_TDO_PIO1_1 &= ~0x7; + LPC_IOCON->JTAG_TDO_PIO1_1 |= 0x1; + LPC_IOCON->JTAG_nTRST_PIO1_2 &= ~0x7; + LPC_IOCON->JTAG_nTRST_PIO1_2 |= 0x1; + LPC_IOCON->ARM_SWDIO_PIO1_3 &= ~0x7; + LPC_IOCON->ARM_SWDIO_PIO1_3 |= 0x1;

dtto

+ + for (;;) { + uart_simple_send("Lorem ipsum dolor\r\n"); + volatile int u; + for (u = 0; u < 10000; u++); + } +} diff --git a/app/arm/nazdar1311/uart.c b/app/arm/nazdar1311/uart.c new file mode 100644 index 0000000..f896b4d --- /dev/null +++ b/app/arm/nazdar1311/uart.c

Nebylo by tohle lepsi spis jako knihovna?

@@ -0,0 +1,101 @@ +#include <lpc13xx.h> +#include "uart.h" + +#define BIT(n) (1 << (n)) + +void uart_simple_init(int baudrate) {

Tahle funkce ma DOSovy konce radku, zbytek souboru ne. V ostatnich souborech je v koncich rakdu taky trochu zmanek.

+ uint32_t Fdiv; + uint32_t regVal; + + LPC_IOCON->PIO1_6 &= ~0x07; /* UART I/O config */ + LPC_IOCON->PIO1_6 |= 0x01; /* UART RXD */ + LPC_IOCON->PIO1_7 &= ~0x07; + LPC_IOCON->PIO1_7 |= 0x01; /* UART TXD */ + + /* Enable UART clock */ + LPC_SYSCON->SYSAHBCLKCTRL |= BIT(12); + LPC_SYSCON->UARTCLKDIV = 0x1; /* divided by 1 */ + + LPC_UART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ + regVal = LPC_SYSCON->UARTCLKDIV; + Fdiv = (((IRC_OSC/LPC_SYSCON->SYSAHBCLKDIV)/regVal)/16)/baudrate ; /*baud rate */ + + LPC_UART->FDR = 0x10; /* No Fractional Divider */ + LPC_UART->DLM = Fdiv / 256; + LPC_UART->DLL = Fdiv % 256; + LPC_UART->LCR = 0x03; /* DLAB = 0 */ + LPC_UART->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ + LPC_UART->MCR = 0x0; /* disable auto-flow controll */ + + /* Read to clear the line status. */ + regVal = LPC_UART->LSR; + + /* Ensure a clean start, no data in either TX or RX FIFO. */ + while ( (LPC_UART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) ); + while ( LPC_UART->LSR & LSR_RDR ) + { + regVal = LPC_UART->RBR; /* Dump data from RX FIFO */ + } + return; +} + +void uart_simple_send(char *str) +{ + char ch; + while ((ch = *str)) + { + if (ch == 0) + break; + uart_simple_send_ch(ch); + str++; + } +} + +void uart_simple_send_ch(char ch) +{ + /* active waiting loop */ + while ( !(LPC_UART->LSR & LSR_THRE) ); + + LPC_UART->THR = ch; +} + +void uart_simple_send_i(int number) +{ + char snum[12]; + snum[11] = 0; + uint8_t i = 10; + + if ( number < 0 ) + { + number *= -1; + snum[i--] = '-'; + } + if ( number == 0 ) + snum[i--] = '0'; + else + while ( number != 0 ){ + snum[i--] = (char)(48 + (number % 10)); + number = number / 10; + } + uart_simple_send(&snum[++i]); +} + +void uart_simple_send_h(uint32_t number) +{ + char snum[9]; + snum[8] = 0; + uint8_t i = 7; + + if ( number == 0 ) + snum[i--] = '0'; + else + while ( number != 0 ){ + snum[i] = (char)(48 + (number % 16)); + if (snum[i] > 57) + snum[i] += 7; + i--; + number = number / 16; + } + uart_simple_send(&snum[++i]); +} + diff --git a/app/arm/nazdar1311/uart.h b/app/arm/nazdar1311/uart.h new file mode 100644 index 0000000..c1b8cb0 --- /dev/null +++ b/app/arm/nazdar1311/uart.h @@ -0,0 +1,47 @@ +#ifndef UART_H +#define UART_H + +/* Internal RC oscillator frequency */ +#define IRC_OSC (12000000UL) + +/* Some Uart rubbish */ +#define IER_RBR 0x01 +#define IER_THRE 0x02 +#define IER_RLS 0x04 + +#define IIR_PEND 0x01 +#define IIR_RLS 0x03 +#define IIR_RDA 0x02 +#define IIR_CTI 0x06 +#define IIR_THRE 0x01 + +#define LSR_RDR 0x01 +#define LSR_OE 0x02 +#define LSR_PE 0x04 +#define LSR_FE 0x08 +#define LSR_BI 0x10 +#define LSR_THRE 0x20 +#define LSR_TEMT 0x40 +#define LSR_RXFE 0x80 + +/** Init UART with desired baud-rate, using active-wait. + */ +void uart_simple_init(int baudrate); + +/** Send null-terminated string, using active-wait. + */ +void uart_simple_send(char *str); + +/** Send one character, using active-wait. + */ +void uart_simple_send_ch(char ch); + +/** Send number, using active-wait. + */ +void uart_simple_send_i(int number); + +/** Send number in hexadecimal format, using active-wait. + */ +void uart_simple_send_h(uint32_t number); + +#endif /* UART_H */ diff --git a/arch/arm/mach-lpc_m3/Makefile b/arch/arm/mach-lpc_m3/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/arch/arm/mach-lpc_m3/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/arch/arm/mach-lpc_m3/Makefile.omk b/arch/arm/mach-lpc_m3/Makefile.omk new file mode 100644 index 0000000..2ebd5c8 --- /dev/null +++ b/arch/arm/mach-lpc_m3/Makefile.omk @@ -0,0 +1 @@ +SUBDIRS = defines libs diff --git a/arch/arm/mach-lpc_m3/defines/Makefile b/arch/arm/mach-lpc_m3/defines/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/arch/arm/mach-lpc_m3/defines/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/arch/arm/mach-lpc_m3/defines/Makefile.omk b/arch/arm/mach-lpc_m3/defines/Makefile.omk new file mode 100644 index 0000000..176b8a6 --- /dev/null +++ b/arch/arm/mach-lpc_m3/defines/Makefile.omk @@ -0,0 +1,2 @@ +# -*- makefile -*- +include_HEADERS = $(notdir $(wildcard $(SOURCES_DIR)/*.h)) diff --git a/arch/arm/mach-lpc_m3/defines/core_cm3.h b/arch/arm/mach-lpc_m3/defines/core_cm3.h new file mode 100644 index 0000000..b294e3d --- /dev/null +++ b/arch/arm/mach-lpc_m3/defines/core_cm3.h @@ -0,0 +1,978 @@ +/****************************************************************************//** + * @file : core_cm3.h + * @brief : CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version : V1.20 simplified for GCC only + * @date : 31. March 2010 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-Mx + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +/** + * Lint configuration \n + * ----------------------- \n + * + * The following Lint messages will be suppressed and not shown: \n + * \n + * --- Error 10: --- \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' \n + * \n + * --- Error 530: --- \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n + * \n + * --- Error 550: --- \n + * __regBasePri = (basePri & 0x1ff); \n + * } \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n + * \n + * --- Error 754: --- \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n + * \n + * --- Error 750: --- \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n + * \n + * --- Error 528: --- \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n + * \n + * --- Error 751: --- \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n + * \n + * \n + * Note: To re-enable a Message, insert a space before 'lint' * \n + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +#include <stdint.h> /* Include standard types */ + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus +#define __I volatile /*!< defines 'read only' permissions */ +#else +#define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ + + +/* System Reset */ +#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */ +#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */ +#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */ +#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */ + +/* Core Debug */ +#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */ +#define ITM_TCR_ITMENA 1 /*!< ITM enable */ + + + + +/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Software Trigger Interrupt Register */ +} NVIC_Type; + + +/* memory mapping struct for System Control Block */ +typedef struct +{ + __I uint32_t CPUID; /*!< CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< System Control Register */ + __IO uint32_t CCR; /*!< Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Processor Feature Register */ + __I uint32_t DFR; /*!< Debug Feature Register */ + __I uint32_t ADR; /*!< Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< ISA Feature Register */ +} SCB_Type; + + +/* memory mapping struct for SysTick */ +typedef struct +{ + __IO uint32_t CTRL; /*!< SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< SysTick Current Value Register */ + __I uint32_t CALIB; /*!< SysTick Calibration Register */ +} SysTick_Type; + + +/* memory mapping structur for ITM */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< ITM Integration Write Register */ + __IO uint32_t IRR; /*!< ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< ITM Lock Access Register */ + __IO uint32_t LSR; /*!< ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< ITM Product ID Registers */ + __I uint32_t PID5; + __I uint32_t PID6; + __I uint32_t PID7; + __I uint32_t PID0; + __I uint32_t PID1; + __I uint32_t PID2; + __I uint32_t PID3; + __I uint32_t CID0; + __I uint32_t CID1; + __I uint32_t CID2; + __I uint32_t CID3; +} ITM_Type; + + +/* memory mapped struct for Interrupt Type */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + + +/* Memory Protection Unit */ +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +typedef struct +{ + __I uint32_t TYPE; /*!< MPU Type Register */ + __IO uint32_t CTRL; /*!< MPU Control Register */ + __IO uint32_t RNR; /*!< MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; +#endif + + +/* Core Debug Register */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +/* ################### Compiler specific Intrinsics ########################### */ + +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +static __INLINE uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +static __INLINE uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @param none + * @return uint32_t BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** + * @brief Set the Base Priority value + * + * @param uint32_t BasePriority + * @return none + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +/** + * @brief Return the Fault Mask value + * + * @param none + * @return uint32_t FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + * @brief Set the Fault Mask value + * + * @param uint32_t faultMask value + * @return none + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @param none +* @return uint32_t Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + +/** + * @brief Reverse byte order in integer value + * + * @param uint32_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in integer value + */ +static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +static __INLINE uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * Reverse byte order in signed short value with sign extension to integer + * + * @param int16_t value to reverse + * @return int32_t reversed value + * + * @brief Reverse byte order in signed short value with sign extension to integer + */ +static __INLINE int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param uint32_t value to reverse + * @return uint32_t reversed value + * + * Reverse bit order of value + */ +static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive + * + * @param uint8_t* address + * @return uint8_t value of (*address) + * + * Exclusive LDR command + */ +static __INLINE uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive + * + * @param uint16_t* address + * @return uint16_t value of (*address) + * + * Exclusive LDR command + */ +static __INLINE uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive + * + * @param uint32_t* address + * @return uint32_t value of (*address) + * + * Exclusive LDR command + */ +static __INLINE uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive + * + * @param uint8_t *address + * @param uint8_t value to store + * @return uint32_t successful / failed + * + * Exclusive STR command + */ +static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive + * + * @param uint16_t *address + * @param uint16_t value to store + * @return uint32_t successful / failed + * + * Exclusive STR command + */ +static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive + * + * @param uint32_t *address + * @param uint32_t value to store + * @return uint32_t successful / failed + * + * Exclusive STR command + */ +static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/* ########################## NVIC functions #################################### */ + + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param uint32_t priority_grouping is priority grouping field + * @return none + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */ + reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @param none + * @return uint32_t priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn_Type IRQn specifies the interrupt number + * @return none + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn_Type IRQn is the positive number of the external interrupt + * @return none + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn_Type IRQn is the number of the device specifc interrupt + * @return uint32_t 1 if pending interrupt else 0 + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return none + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return none + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return uint32_t 1 if active else 0 + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @param priority is the priority for the interrupt + * @return none + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. \n + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return uint32_t priority is the priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param uint32_t PriorityGroup is the used priority group + * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0) + * @param uint32_t SubPriority is the sub priority value (starting from 0) + * @return uint32_t the priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param uint32_t Priority the priority for the interrupt + * @param uint32_t PrioGroup is the used priority group + * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0) + * @param uint32_t* pSubPrio is the sub priority value (starting from 0) + * @return none + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/* SysTick constants */ +#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */ +#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */ +#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */ +#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */ + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param uint32_t ticks is the number of ticks between two interrupts + * @return none + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = (0x00); /* Load the SysTick Counter Value */ + SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * @param none + * @return none + * + * Initialize a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + + +/* ################################## Debug Output function ############################################ */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param uint32_t character to output + * @return uint32_t input character + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (ch == '\n') ITM_SendChar('\r'); + + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) && + (ITM->TCR & ITM_TCR_ITMENA) && + (ITM->TER & (1UL << 0)) ) + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/arch/arm/mach-lpc_m3/defines/lpc13xx.h b/arch/arm/mach-lpc_m3/defines/lpc13xx.h new file mode 100644 index 0000000..4d71c34 --- /dev/null +++ b/arch/arm/mach-lpc_m3/defines/lpc13xx.h @@ -0,0 +1,493 @@ +/**************************************************************************//** + * @file LPC13xx.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * NXP LPC13xx Device Series + * @version V1.01 + * @date 19. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __LPC13xx_H__ +#define __LPC13xx_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** LPC13xx Specific Interrupt Numbers *******************************************************/ + WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */ + WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */ + WAKEUP2_IRQn = 2, + WAKEUP3_IRQn = 3, + WAKEUP4_IRQn = 4, + WAKEUP5_IRQn = 5, + WAKEUP6_IRQn = 6, + WAKEUP7_IRQn = 7, + WAKEUP8_IRQn = 8, + WAKEUP9_IRQn = 9, + WAKEUP10_IRQn = 10, + WAKEUP11_IRQn = 11, + WAKEUP12_IRQn = 12, + WAKEUP13_IRQn = 13, + WAKEUP14_IRQn = 14, + WAKEUP15_IRQn = 15, + WAKEUP16_IRQn = 16, + WAKEUP17_IRQn = 17, + WAKEUP18_IRQn = 18, + WAKEUP19_IRQn = 19, + WAKEUP20_IRQn = 20, + WAKEUP21_IRQn = 21, + WAKEUP22_IRQn = 22, + WAKEUP23_IRQn = 23, + WAKEUP24_IRQn = 24, + WAKEUP25_IRQn = 25, + WAKEUP26_IRQn = 26, + WAKEUP27_IRQn = 27, + WAKEUP28_IRQn = 28, + WAKEUP29_IRQn = 29, + WAKEUP30_IRQn = 30, + WAKEUP31_IRQn = 31, + WAKEUP32_IRQn = 32, + WAKEUP33_IRQn = 33, + WAKEUP34_IRQn = 34, + WAKEUP35_IRQn = 35, + WAKEUP36_IRQn = 36, + WAKEUP37_IRQn = 37, + WAKEUP38_IRQn = 38, + WAKEUP39_IRQn = 39, + I2C_IRQn = 40, /*!< I2C Interrupt */ + TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */ + TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */ + TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */ + TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */ + SSP_IRQn = 45, /*!< SSP Interrupt */ + UART_IRQn = 46, /*!< UART Interrupt */ + USB_IRQn = 47, /*!< USB Regular Interrupt */ + USB_FIQn = 48, /*!< USB Fast Interrupt */ + ADC_IRQn = 49, /*!< A/D Converter Interrupt */ + WDT_IRQn = 50, /*!< Watchdog timer Interrupt */ + BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */ + EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */ + EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */ + EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */ + EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ +//#include "system_LPC13xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */ + __IO uint32_t PRESETCTRL; + __IO uint32_t SYSPLLCTRL; /* Sys PLL control */ + __IO uint32_t SYSPLLSTAT; + __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */ + __IO uint32_t USBPLLSTAT; + uint32_t RESERVED0[2]; + + __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */ + __IO uint32_t WDTOSCCTRL; + __IO uint32_t IRCCTRL; + uint32_t RESERVED1[1]; + __IO uint32_t SYSRESSTAT; /* Offset 0x30 */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */ + __IO uint32_t SYSPLLCLKUEN; + __IO uint32_t USBPLLCLKSEL; + __IO uint32_t USBPLLCLKUEN; + uint32_t RESERVED3[8]; + + __IO uint32_t MAINCLKSEL; /* Offset 0x70 */ + __IO uint32_t MAINCLKUEN; + __IO uint32_t SYSAHBCLKDIV; + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */ + uint32_t RESERVED5[4]; + __IO uint32_t SSPCLKDIV; + __IO uint32_t UARTCLKDIV; + uint32_t RESERVED6[4]; + __IO uint32_t TRACECLKDIV; + + __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */ + uint32_t RESERVED7[3]; + + __IO uint32_t USBCLKSEL; /* Offset 0xC0 */ + __IO uint32_t USBCLKUEN; + __IO uint32_t USBCLKDIV; + uint32_t RESERVED8[1]; + __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */ + __IO uint32_t WDTCLKUEN; + __IO uint32_t WDTCLKDIV; + uint32_t RESERVED9[1]; + __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */ + __IO uint32_t CLKOUTUEN; + __IO uint32_t CLKOUTDIV; + uint32_t RESERVED10[5]; + + __IO uint32_t PIOPORCAP0; /* Offset 0x100 */ + __IO uint32_t PIOPORCAP1; + uint32_t RESERVED11[18]; + + __IO uint32_t BODCTRL; /* Offset 0x150 */ + uint32_t RESERVED12[1]; + __IO uint32_t SYSTCKCAL; + uint32_t RESERVED13[41]; + + __IO uint32_t STARTAPRP0; /* Offset 0x200 */ + __IO uint32_t STARTERP0; + __IO uint32_t STARTRSRP0CLR; + __IO uint32_t STARTSRP0; + __IO uint32_t STARTAPRP1; + __IO uint32_t STARTERP1; + __IO uint32_t STARTRSRP1CLR; + __IO uint32_t STARTSRP1; + uint32_t RESERVED14[4]; + + __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */ + __IO uint32_t PDAWAKECFG; + __IO uint32_t PDRUNCFG; + uint32_t RESERVED15[110]; + __I uint32_t DEVICE_ID; +} LPC_SYSCON_TypeDef; + + +/*------------- Pin Connect Block (IOCON) --------------------------------*/ +typedef struct +{ + __IO uint32_t PIO2_6; + uint32_t RESERVED0[1]; + __IO uint32_t PIO2_0; + __IO uint32_t RESET_PIO0_0; + __IO uint32_t PIO0_1; + __IO uint32_t PIO1_8; + uint32_t RESERVED1[1]; + __IO uint32_t PIO0_2; + + __IO uint32_t PIO2_7; + __IO uint32_t PIO2_8; + __IO uint32_t PIO2_1; + __IO uint32_t PIO0_3; + __IO uint32_t PIO0_4; + __IO uint32_t PIO0_5; + __IO uint32_t PIO1_9; + __IO uint32_t PIO3_4; + + __IO uint32_t PIO2_4; + __IO uint32_t PIO2_5; + __IO uint32_t PIO3_5; + __IO uint32_t PIO0_6; + __IO uint32_t PIO0_7; + __IO uint32_t PIO2_9; + __IO uint32_t PIO2_10; + __IO uint32_t PIO2_2; + + __IO uint32_t PIO0_8; + __IO uint32_t PIO0_9; + __IO uint32_t JTAG_TCK_PIO0_10; + __IO uint32_t PIO1_10; + __IO uint32_t PIO2_11; + __IO uint32_t JTAG_TDI_PIO0_11; + __IO uint32_t JTAG_TMS_PIO1_0; + __IO uint32_t JTAG_TDO_PIO1_1; + + __IO uint32_t JTAG_nTRST_PIO1_2; + __IO uint32_t PIO3_0; + __IO uint32_t PIO3_1; + __IO uint32_t PIO2_3; + __IO uint32_t ARM_SWDIO_PIO1_3; + __IO uint32_t PIO1_4; + __IO uint32_t PIO1_11; + __IO uint32_t PIO3_2; + + __IO uint32_t PIO1_5; + __IO uint32_t PIO1_6; + __IO uint32_t PIO1_7; + __IO uint32_t PIO3_3; + __IO uint32_t SCKLOC; /* For HB1 only, new feature */ +} LPC_IOCON_TypeDef; + + +/*------------- Power Management Unit (PMU) --------------------------*/ +typedef struct +{ + __IO uint32_t PCON; + __IO uint32_t GPREG0; + __IO uint32_t GPREG1; + __IO uint32_t GPREG2; + __IO uint32_t GPREG3; + __IO uint32_t GPREG4; +} LPC_PMU_TypeDef; + + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + union { + __IO uint32_t MASKED_ACCESS[4096]; + struct { + uint32_t RESERVED0[4095]; + __IO uint32_t DATA; + }; + }; + uint32_t RESERVED1[4096]; + __IO uint32_t DIR; + __IO uint32_t IS; + __IO uint32_t IBE; + __IO uint32_t IEV; + __IO uint32_t IE; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t IC; +} LPC_GPIO_TypeDef; + + +/*------------- Timer (TMR) --------------------------------------------------*/ +typedef struct +{ + __IO uint32_t IR; + __IO uint32_t TCR; + __IO uint32_t TC; + __IO uint32_t PR; + __IO uint32_t PC; + __IO uint32_t MCR; + __IO uint32_t MR0; + __IO uint32_t MR1; + __IO uint32_t MR2; + __IO uint32_t MR3; + __IO uint32_t CCR; + __I uint32_t CR0; + uint32_t RESERVED1[3]; + __IO uint32_t EMR; + uint32_t RESERVED2[12]; + __IO uint32_t CTCR; + __IO uint32_t PWMC; +} LPC_TMR_TypeDef; + +/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ +typedef struct +{ + union { + __I uint32_t RBR; + __O uint32_t THR; + __IO uint32_t DLL; + }; + union { + __IO uint32_t DLM; + __IO uint32_t IER; + }; + union { + __I uint32_t IIR; + __O uint32_t FCR; + }; + __IO uint32_t LCR; + __IO uint32_t MCR; + __I uint32_t LSR; + __I uint32_t MSR; + __IO uint32_t SCR; + __IO uint32_t ACR; + __IO uint32_t ICR; + __IO uint32_t FDR; + uint32_t RESERVED0; + __IO uint32_t TER; + uint32_t RESERVED1[6]; + __IO uint32_t RS485CTRL; + __IO uint32_t ADRMATCH; + __IO uint32_t RS485DLY; + __I uint32_t FIFOLVL; +} LPC_UART_TypeDef; + +/*------------- Synchronous Serial Communication (SSP) -----------------------*/ +typedef struct +{ + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t DR; + __I uint32_t SR; + __IO uint32_t CPSR; + __IO uint32_t IMSC; + __IO uint32_t RIS; + __IO uint32_t MIS; + __IO uint32_t ICR; +} LPC_SSP_TypeDef; + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +typedef struct +{ + __IO uint32_t CONSET; + __I uint32_t STAT; + __IO uint32_t DAT; + __IO uint32_t ADR0; + __IO uint32_t SCLH; + __IO uint32_t SCLL; + __O uint32_t CONCLR; + __IO uint32_t MMCTRL; + __IO uint32_t ADR1; + __IO uint32_t ADR2; + __IO uint32_t ADR3; + __I uint32_t DATA_BUFFER; + __IO uint32_t MASK0; + __IO uint32_t MASK1; + __IO uint32_t MASK2; + __IO uint32_t MASK3; +} LPC_I2C_TypeDef; + +/*------------- Watchdog Timer (WDT) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t MOD; + __IO uint32_t TC; + __O uint32_t FEED; + __I uint32_t TV; +} LPC_WDT_TypeDef; + +/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t GDR; + uint32_t RESERVED0; + __IO uint32_t INTEN; + __I uint32_t DR0; + __I uint32_t DR1; + __I uint32_t DR2; + __I uint32_t DR3; + __I uint32_t DR4; + __I uint32_t DR5; + __I uint32_t DR6; + __I uint32_t DR7; + __I uint32_t STAT; +} LPC_ADC_TypeDef; + + +/*------------- Universal Serial Bus (USB) -----------------------------------*/ +typedef struct +{ + __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ + __IO uint32_t DevIntEn; + __O uint32_t DevIntClr; + __O uint32_t DevIntSet; + + __O uint32_t CmdCode; /* USB Device SIE Command Registers */ + __I uint32_t CmdData; + + __I uint32_t RxData; /* USB Device Transfer Registers */ + __O uint32_t TxData; + __I uint32_t RxPLen; + __O uint32_t TxPLen; + __IO uint32_t Ctrl; + __O uint32_t DevFIQSel; +} LPC_USB_TypeDef; + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000) +#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000) +#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000) +#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000) +#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000) +#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) + +/* AHB peripherals */ +#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000) +#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000) +#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) +#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE ) +#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE) +#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE) +#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE) +#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE) +#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) +#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) +#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) +#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) +#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) + +#endif // __LPC13xx_H__ diff --git a/arch/arm/mach-lpc_m3/libs/Makefile b/arch/arm/mach-lpc_m3/libs/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/arch/arm/mach-lpc_m3/libs/Makefile.omk b/arch/arm/mach-lpc_m3/libs/Makefile.omk new file mode 100644 index 0000000..5baf5ed --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/Makefile.omk @@ -0,0 +1,3 @@ +# -*- makefile -*- + +SUBDIRS = $(ALL_OMK_SUBDIRS) diff --git a/arch/arm/mach-lpc_m3/libs/boot/Makefile b/arch/arm/mach-lpc_m3/libs/boot/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/boot/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/arch/arm/mach-lpc_m3/libs/boot/Makefile.omk b/arch/arm/mach-lpc_m3/libs/boot/Makefile.omk new file mode 100644 index 0000000..fcecd6c --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/boot/Makefile.omk @@ -0,0 +1,3 @@ +# -*- makefile -*- + +lib_obj_SOURCES = crt0_13xx.c initarray.c diff --git a/arch/arm/mach-lpc_m3/libs/boot/crt0_13xx.c b/arch/arm/mach-lpc_m3/libs/boot/crt0_13xx.c new file mode 100644 index 0000000..e1df13b --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/boot/crt0_13xx.c @@ -0,0 +1,236 @@ +/** + * crt0.c + * LPC13xx (ARM Cortex M3) family startup code + * + * adapted from startup_LPC17xx.c + * by Marek Peca <mp@duch.cz> 2010/06 + * + * ( file : startup_LPC17xx.c ) + * ( brief : CMSIS Cortex-M3 Core Device Startup File ) + * ( version : V1.01 ) + * ( date : 4. Feb. 2009 ) + * ( Copyright (C) 2009 ARM Limited. All rights reserved. ) + * + * ( ARM Limited (ARM) is supplying this software for use with Cortex-Mx ) + * ( processor based microcontrollers. This file can be freely distributed ) + * ( within development tools that are supporting such ARM based processors. ) + */ + +#include <sys/types.h> +#include <lpc13xx.h> + +#define WEAK __attribute__((weak)) + +/* System exception vector handler */ +void WEAK Reset_Handler(); /* Reset Handler */ +void WEAK NMI_Handler(); /* NMI Handler */ +void WEAK HardFault_Handler(); /* Hard Fault Handler */ +void WEAK MemManage_Handler(); /* MPU Fault Handler */ +void WEAK BusFault_Handler(); /* Bus Fault Handler */ +void WEAK UsageFault_Handler(); /* Usage Fault Handler */ +void WEAK SVC_Handler(); /* SVCall Handler */ +void WEAK DebugMon_Handler(); /* Debug Monitor Handler */ +void WEAK PendSV_Handler(); /* PendSV Handler */ +void WEAK SysTick_Handler(); /* SysTick Handler */ + +/* External interrupt vector handler */ +void WEAK WAKEUP_IRQHandler(); +void WEAK I2C_IRQHandler(); +void WEAK TIMER16_0_IRQHandler(); +void WEAK TIMER16_1_IRQHandler(); +void WEAK TIMER32_0_IRQHandler(); +void WEAK TIMER32_1_IRQHandler(); +void WEAK SSP_IRQHandler(); +void WEAK UART_IRQHandler(); +void WEAK USB_IRQHandler(); +void WEAK USB_FIQHandler(); +void WEAK ADC_IRQHandler(); +void WEAK WDT_IRQHandler(); +void WEAK BOD_IRQHandler(); +void WEAK FMC_IRQHandler(); +void WEAK PIOINT3_IRQHandler(); +void WEAK PIOINT2_IRQHandler(); +void WEAK PIOINT1_IRQHandler(); +void WEAK PIOINT0_IRQHandler(); + +/** memory map pointers (defined in ldscript) **/ +extern uint32_t _data, _edata, _datainit; +extern uint32_t __bss_start, __bss_end__; +extern uint32_t _stack; + +/** function prototypes **/ +extern void WEAK _memory_init(); +extern void WEAK __libc_init_array(); +////void _start() __attribute__((__interrupt__)); +void _start(); +extern int main(); + +/* + * The minimal vector table for a Cortex M3. Note that the proper constructs + * must be placed on this to ensure that it ends up at physical address + * 0x00000000. + */ +__attribute__((section(".ivec"))) + void (* const _vectors[])() = +{ + /* Cortex M3 common */ + (void (*)())&_stack, /* The initial stack pointer */ + _start, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + /* LPC13xx specific interrupts */ + WAKEUP_IRQHandler, /* 16 0 Wake-up on pin PIO0_0 */ + WAKEUP_IRQHandler, /* 17 1 Wake-up on pin PIO0_1 */ + WAKEUP_IRQHandler, /* 18 2 Wake-up on pin PIO0_2 */ + WAKEUP_IRQHandler, /* 19 3 Wake-up on pin PIO0_3 */ + WAKEUP_IRQHandler, /* 20 4 Wake-up on pin PIO0_4 */ + WAKEUP_IRQHandler, /* 21 5 Wake-up on pin PIO0_5 */ + WAKEUP_IRQHandler, /* 22 6 Wake-up on pin PIO0_6 */ + WAKEUP_IRQHandler, /* 23 7 Wake-up on pin PIO0_7 */ + WAKEUP_IRQHandler, /* 24 8 Wake-up on pin PIO0_8 */ + WAKEUP_IRQHandler, /* 25 9 Wake-up on pin PIO0_9 */ + WAKEUP_IRQHandler, /* 26 10 Wake-up on pin PIO0_10 */ + WAKEUP_IRQHandler, /* 27 11 Wake-up on pin PIO0_11 */ + WAKEUP_IRQHandler, /* 28 12 Wake-up on pin PIO1_0 */ + WAKEUP_IRQHandler, /* 29 13 Wake-up on pin PIO1_1 */ + WAKEUP_IRQHandler, /* 30 14 Wake-up on pin PIO1_2 */ + WAKEUP_IRQHandler, /* 31 15 Wake-up on pin PIO1_3 */ + WAKEUP_IRQHandler, /* 32 16 Wake-up on pin PIO1_4 */ + WAKEUP_IRQHandler, /* 33 17 Wake-up on pin PIO1_5 */ + WAKEUP_IRQHandler, /* 34 18 Wake-up on pin PIO1_6 */ + WAKEUP_IRQHandler, /* 35 19 Wake-up on pin PIO1_7 */ + WAKEUP_IRQHandler, /* 36 20 Wake-up on pin PIO1_8 */ + WAKEUP_IRQHandler, /* 37 21 Wake-up on pin PIO1_9 */ + WAKEUP_IRQHandler, /* 38 22 Wake-up on pin PIO1_10 */ + WAKEUP_IRQHandler, /* 39 23 Wake-up on pin PIO1_11 */ + WAKEUP_IRQHandler, /* 40 24 Wake-up on pin PIO2_0 */ + WAKEUP_IRQHandler, /* 41 25 Wake-up on pin PIO2_1 */ + WAKEUP_IRQHandler, /* 42 26 Wake-up on pin PIO2_2 */ + WAKEUP_IRQHandler, /* 43 27 Wake-up on pin PIO2_3 */ + WAKEUP_IRQHandler, /* 44 28 Wake-up on pin PIO2_4 */ + WAKEUP_IRQHandler, /* 45 29 Wake-up on pin PIO2_5 */ + WAKEUP_IRQHandler, /* 46 30 Wake-up on pin PIO2_6 */ + WAKEUP_IRQHandler, /* 47 31 Wake-up on pin PIO2_7 */ + WAKEUP_IRQHandler, /* 48 32 Wake-up on pin PIO2_8 */ + WAKEUP_IRQHandler, /* 49 33 Wake-up on pin PIO2_9 */ + WAKEUP_IRQHandler, /* 50 34 Wake-up on pin PIO2_10 */ + WAKEUP_IRQHandler, /* 51 35 Wake-up on pin PIO2_11 */ + WAKEUP_IRQHandler, /* 52 36 Wake-up on pin PIO3_0 */ + WAKEUP_IRQHandler, /* 53 37 Wake-up on pin PIO3_1 */ + WAKEUP_IRQHandler, /* 54 38 Wake-up on pin PIO3_2 */ + WAKEUP_IRQHandler, /* 55 39 Wake-up on pin PIO3_3 */ + I2C_IRQHandler, /* 56 40 I2C0 SI (state change) */ + TIMER16_0_IRQHandler, /* 57 41 CT16B0 16 bit timer 0 */ + TIMER16_1_IRQHandler, /* 58 42 CT16B1 16 bit timer 1 */ + TIMER32_0_IRQHandler, /* 59 43 CT32B0 32 bit timer 0 */ + TIMER32_1_IRQHandler, /* 60 44 CT32B1 32 bit timer 1 */ + SSP_IRQHandler, /* 61 45 SSP */ + UART_IRQHandler, /* 62 46 UART */ + USB_IRQHandler, /* 63 47 USB IRQ low priority */ + USB_FIQHandler, /* 64 48 USB FIQ high priority */ + ADC_IRQHandler, /* 65 49 ADC end of conversion */ + WDT_IRQHandler, /* 66 50 Watchdog interrupt (WDINT) */ + BOD_IRQHandler, /* 67 51 BOD Brown-out detect */ + FMC_IRQHandler, /* 68 52 Reserved also marked as IP2111 Flash Memory */ + PIOINT3_IRQHandler, /* 69 53 PIO_3 GPIO interrupt status of port 3 */ + PIOINT2_IRQHandler, /* 70 54 PIO_2 GPIO interrupt status of port 2 */ + PIOINT1_IRQHandler, /* 71 55 PIO_1 GPIO interrupt status of port 1 */ + PIOINT0_IRQHandler, /* 72 56 PIO_0 GPIO interrupt status of port 0 */ +}; + +/* + * startup code (Reset Handler) + */ +void _start() { + uint32_t *src, *dst; + + /* + * External memory initialization (only if _memory_init linked) + * (can not be called from init_array, must precede data initialization) + */ + if (_memory_init) + _memory_init(); + + /* Copy initialized data to its execution address in RAM */ + if (&_datainit != &_data) { /* _datainit == _data indicates RAM, ie. no need of copying */ + for (src = &_datainit, dst = &_data; dst < &_edata; src++, dst++) + *dst = *src; + } + + /* clear .bss */ + for (dst = &__bss_start; dst < &__bss_end__; dst++) + *dst = 0; + + /* + * remap IRQ vector or not, depending on their RAM/ROM location + */ + LPC_SYSCON->SYSMEMREMAP = 1 + (&_vectors == (uint32_t*)0x0); + + /* Call init functions in .init_array section (only if __libc_init_array exists) */ + if (__libc_init_array) + __libc_init_array(); + + /* set irq table */ + SCB->VTOR=0x10000000; + + /* Call the application's entry point. */ + main(); + + /* Requiescat In Pacem */ + for (;;); +} + +/* + * This is the code that gets called when the processor receives an unexpected + * interrupt. This simply enters an infinite loop, preserving the system state + * for examination by a debugger. + */ +void Default_Handler() { + for (;;); +} + +/* + * Provide weak aliases for each Exception handler to the Default_Handler. + * As they are weak aliases, any function with the same name will override + * this definition. + */ +#pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */ +#pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */ +#pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */ +#pragma weak SVC_Handler = Default_Handler /* SVCall Handler */ +#pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */ +#pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */ +#pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */ + +/* External interrupt vector handler */ +#pragma weak WAKEUP_IRQHandler = Default_Handler +#pragma weak I2C_IRQHandler = Default_Handler +#pragma weak TIMER16_0_IRQHandler = Default_Handler +#pragma weak TIMER16_1_IRQHandler = Default_Handler +#pragma weak TIMER32_0_IRQHandler = Default_Handler +#pragma weak TIMER32_1_IRQHandler = Default_Handler +#pragma weak SSP_IRQHandler = Default_Handler +#pragma weak UART_IRQHandler = Default_Handler +#pragma weak USB_IRQHandler = Default_Handler +#pragma weak USB_FIQHandler = Default_Handler +#pragma weak ADC_IRQHandler = Default_Handler +#pragma weak WDT_IRQHandler = Default_Handler +#pragma weak BOD_IRQHandler = Default_Handler +#pragma weak FMC_IRQHandler = Default_Handler +#pragma weak PIOINT3_IRQHandler = Default_Handler +#pragma weak PIOINT2_IRQHandler = Default_Handler +#pragma weak PIOINT1_IRQHandler = Default_Handler +#pragma weak PIOINT0_IRQHandler = Default_Handler diff --git a/arch/arm/mach-lpc_m3/libs/boot/initarray.c b/arch/arm/mach-lpc_m3/libs/boot/initarray.c new file mode 120000 index 0000000..fd113a0 --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/boot/initarray.c @@ -0,0 +1 @@ +../../../mach-lpc23xx/libs/boot/initarray.c \ No newline at end of file diff --git a/arch/arm/mach-lpc_m3/libs/ldscripts/Makefile b/arch/arm/mach-lpc_m3/libs/ldscripts/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/ldscripts/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/arch/arm/mach-lpc_m3/libs/ldscripts/Makefile.omk b/arch/arm/mach-lpc_m3/libs/ldscripts/Makefile.omk new file mode 100644 index 0000000..e47cf33 --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/ldscripts/Makefile.omk @@ -0,0 +1,3 @@ +# -*- makefile -*- + +lib_LDSCRIPTS = $(notdir $(wildcard $(SOURCES_DIR)/*.ld*)) diff --git a/arch/arm/mach-lpc_m3/libs/ldscripts/lpc1311.ld-ram b/arch/arm/mach-lpc_m3/libs/ldscripts/lpc1311.ld-ram new file mode 100644 index 0000000..8f6fa11 --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/ldscripts/lpc1311.ld-ram @@ -0,0 +1,28 @@ +/* + * LPC1311 internal RAM (8KB ROM + 4KB RAM) loadable by ISP + */ + +STARTUP(crt0_13xx.o) +INCLUDE board.ld /* Allow to INPUT board specific files */ + +ENTRY(_start) +STACK_SIZE = 0x400; + +/* + 7.8 RAM used by ISP command handler ISP commands use on-chip RAM from + 0x1000 017C to 0x1000 025B. The user could use this area, but the + contents may be lost upon reset. Flash programming commands use the + top 32 bytes of on-chip RAM. The stack is located at RAM top stack + usage is 256 bytes and grows downwards. +*/ + +/* memory definitions */ +MEMORY +{ + RAM_IVEC (rw) : ORIGIN = 0x10000000, LENGTH = 0x017c + RAM_LOAD (rw) : ORIGIN = 0x1000025b, LENGTH = 0x0da5 + RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x1000 +} + +/* include section definitions */ +INCLUDE lpc13xx-ram.ld diff --git a/arch/arm/mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld b/arch/arm/mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld new file mode 100644 index 0000000..3b9eadc --- /dev/null +++ b/arch/arm/mach-lpc_m3/libs/ldscripts/lpc13xx-ram.ld @@ -0,0 +1,104 @@ +/*** + * LPC13xx internal RAM loadable by Philips ISP serial loader + * by Marek Peca <mp@duch.cz> 2009/09, 2010/06 + ***/ + +/*!* to be included by chip-specific linkerscript, containing memory defs *!*/ + +/* section definitions only */ + +SECTIONS +{ + .ivec : + { + *(.ivec) /* interrupt entry points */ + } > RAM_IVEC + + /* first section is .text which is used for code */ + .text : + { + *crt0_13xx.o (.text) /* Startup code */ + *(.text) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + . = ALIGN(4); + _etext = .; + } > RAM_LOAD + + + /* .init_array - pointers to functions called before main */ + PROVIDE(__init_array_start = .); + .init_array : + { + *(.init_array) + . = ALIGN(4); + } > RAM_LOAD = 0 + PROVIDE (__init_array_end = .); + + /* .data section which is used for initialized data */ + .data : + { + _data = .; + _datainit = .; + *(.data) + SORT(CONSTRUCTORS) + . = ALIGN(4); + _edata = .; + } > RAM_LOAD + + /* .bss section which is used for uninitialized data */ + .bss _edata (NOLOAD) : + { + __bss_start = .; + __bss_start__ = .; + *(.bss) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .stack : + { + . += STACK_SIZE; + PROVIDE (_stack = .); + } > RAM + + _end = . ; + PROVIDE (end = .); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/board/arm/lpc1311-mini/Makefile b/board/arm/lpc1311-mini/Makefile new file mode 100644 index 0000000..76b56fd --- /dev/null +++ b/board/arm/lpc1311-mini/Makefile @@ -0,0 +1,14 @@ +# Generic directory or leaf node makefile for OCERA make framework + +ifndef MAKERULES_DIR +MAKERULES_DIR := $(shell ( old_pwd="" ; while [ ! -e Makefile.rules ] ; do if [ "$$old_pwd" = `pwd` ] ; then exit 1 ; else old_pwd=`pwd` ; cd -L .. 2>/dev/null ; fi ; done ; pwd ) ) +endif + +ifeq ($(MAKERULES_DIR),) +all : default +.DEFAULT:: + @echo -e "\nThe Makefile.rules has not been found in this or parent directory\n" +else +include $(MAKERULES_DIR)/Makefile.rules +endif + diff --git a/board/arm/lpc1311-mini/Makefile.omk b/board/arm/lpc1311-mini/Makefile.omk new file mode 100644 index 0000000..99dc2a5 --- /dev/null +++ b/board/arm/lpc1311-mini/Makefile.omk @@ -0,0 +1,6 @@ +# -*- makefile -*- + +SUBDIRS = + +lib_LDSCRIPTS = board.ld +include_HEADERS = system_def.h diff --git a/board/arm/lpc1311-mini/board.ld b/board/arm/lpc1311-mini/board.ld new file mode 100644 index 0000000..20ce73e --- /dev/null +++ b/board/arm/lpc1311-mini/board.ld @@ -0,0 +1 @@ +/* Board specific objects linked with applications */ diff --git a/board/arm/lpc1311-mini/config.lpc1311-mini b/board/arm/lpc1311-mini/config.lpc1311-mini new file mode 100644 index 0000000..fa68d09 --- /dev/null +++ b/board/arm/lpc1311-mini/config.lpc1311-mini @@ -0,0 +1,43 @@ +# -*- makefile -*- + +ARCH=arm +MACH=lpc_m3 +BOARD=lpc1311-mini + +CROSS_COMPILE = arm-elf- +TARGET_ARCH = -mthumb -mcpu=cortex-m3 + +# set ARCH_... & MACH_... C defines +CFLAGS += -DARCH_$(shell echo $(ARCH) | tr a-z A-Z) +CFLAGS += -DMACH_$(shell echo $(MACH) | tr a-z A-Z) +CFLAGS += -D__BIT_TYPES_DEFINED__ + +# Set default C flags. If theese are set elsewhere (e.g. on a command +# line), these default flags are not used. +DEBUG ?= -g +OPTIMIZE ?= -O2 + +#LPCISP=~/projects/cf/lpc21isp_v179/lpc21isp +TOLPC_M3=../../../arch/arm/mach-lpc_m3/tools/tolpc/tolpc -m ../../../arch/arm/mach-lpc_m3/tools/tolpc/lpc13xx.so

A tolpc nam k tomu nedas?

+LPC_BAUD = 115200 +LPC_TTY = /dev/ttyUSB0 +CPU_SYS_KHZ = 12000 + +TOLPC = $(TOLPC_M3) --baud $(LPC_BAUD) --sdev $(LPC_TTY) -q $(CPU_SYS_KHZ) -L -f +LOAD_CMD-ram = $(TOLPC) +LOAD_CMD-flash = load() { $(TOLPC) -bin $$1 $(LPC_TTY) $(LPC_BAUD) $(CPU_SYS_KHZ); }; load + +# This selects linker script +LD_SCRIPT=lpc1311 +DEFAULT_LD_SCRIPT_VARIANT=ram + +#OUTPUT_FORMATS = bin + +### +#CONFIG_USB_BASE=y +#CONFIG_USB_MORE=y +CONFIG_USB_PDIUSB=n +#CONFIG_USB_LPCUSB=y +CONFIG_CMDPROC_TEST=n + +LN_HEADERS=y diff --git a/board/arm/lpc1311-mini/system_def.h b/board/arm/lpc1311-mini/system_def.h new file mode 100644 index 0000000..9022aab --- /dev/null +++ b/board/arm/lpc1311-mini/system_def.h @@ -0,0 +1 @@ +/* rien de rien */

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