January 2018 - PSR - list.iid.ciirc.cvut.cz

Pomoc s výukou předmětu architektury počítačů
by Michal Sojka 25 Jan '18

25 Jan '18

(For Czech students only) Vážení studenti, hledáme magisterské studenty, kteří by byli ochotni pomoct s cvičeními předmětu APO. Jedná se o předmět pro studenty 1. ročníku a problém je, že těch studentů je strašně moc. Nabízíme odměnu formou stipendia. Z vlastní zkušenosti mohu říct, že učením ostatních člověk naučí i sebe. Pokud tedy máte zájem se dovědět něco o fungování počítačů a máte v příštím semestru trochu času, ozvěte se prosím co nejdřív mně nebo Martinu Vajnarovi. Děkuji. -Michal Sojka

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IRC_SR register values in interrupts
by beranj25＠fel.cvut.cz 16 Jan '18

16 Jan '18

In IRC interrupt routine I sometimes get values of IRC_A_MON and IRC_B_MON which are the same as in the interrupt that follows. So the status changes of IRC_{A,B}_MON are like this: [...] 0 2 2 3 3 1 1 0 2 2 3 3 1 1 0 0 2 2 3 3 1 1 0 0 2 3 1 1 0 0 2 2 [...] However, absolute position computed from such status changes seems to be correct. Spin in one direction for a given time then spin in the opposite direction at the same speed for the same time returns to roughly initial value. The difference from initial value is only about tens (one step in absolute position corresponds to one interrupt). Besides, in some cases (tens of hundred thousands interrupts) I read zero from IRC_IRQ_MON, but interrupt source is setup to rising edge, so I'd expect '1' every time. Have anyone encountered similar issue or do you have any explanation for this behavior? Thanks Jaroslav Beran

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controller for semestral project
by mikulpa6＠fel.cvut.cz 16 Jan '18

16 Jan '18

Good afternoon, I have a question in regards to the type of controller for the semestral project. Is it necessary to use PID controller for the PWM DUTY, or is it sufficient to use P controller instead? Thank you Pavol Mikula.

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Termín odevzdávání semestrání práce
by kopecdav＠fel.cvut.cz 16 Jan '18

16 Jan '18

Dobrý den, na cvičení jsme se domlouvali ohledně odevzdání semestrální práce den před zkouškou (tedy zítra 15.1), nicméně nedomluvil jsme se na přesném čase. Kdy bychom se tedy měli dstavit na odevzdání? Mockrát děkuji za odpověď. S pozdravem, David Kopecký

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Semestral work demo
by Toni Lammi 15 Jan '18

15 Jan '18

Hi, If I understood correctly there is a demo session for the semestral work tomorrow (Tue 16th). Is there a time for it already? I haven't received or found any information yet. Best regards, Toni Lammi

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Exam + semestral work
by Toni Lammi 09 Jan '18

09 Jan '18

Hi, I'm an exchange student on course "Real-time systems programming". I heard a rumor (couldn't confirm it myself) that the semestral work needs to be returned before taking the exam. Is this the case? If it is, would it be possible to take the exam prior to returning the semestral work as it would help my schedule with going back to Finland? I would greatly appreciate it. Yours truly, Toni Lammi, toni.j.lammi(a)gmail.com

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Additional positions for exams on 24.01. or 31.01.
by Igor Aleksander Lisowski 09 Jan '18

09 Jan '18

Good evening, I would like to ask if there would be possiblity of adding additional positions for exams on 24.01. or 31.01.? There are only five positions for each exam and they are already full. It would be problematic for me to attend exam on other dates. Best regards, Igor A. Lisowski

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Looking for a partner for the semestral project
by tanweixi＠fel.cvut.cz 03 Jan '18

03 Jan '18

Hello, is there anyone who still does not have a partner for the semestral project? I have been unable to find anyone free to work with me since the holidays. Please email me if you are free to work with me. Thank you very much in advance. Best regards, Tan Wei Xin

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Spolupracovník na semestrálku a zápočet
by Jiří Cvrček 02 Jan '18

02 Jan '18

Přeji dobrý večer, chtěl bych se zeptat, zda je podmínkou zápočtu odevzdání všech úloh, nebo stačí zisk 14b. A pak taky poptat, zda je ještě nějaký opožděný "expert" jako já, který nemá dvojici na semestrálku a měl by zájem se do toho vrhnout. S pozdravem, Jiří Cvrček

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The second "dcsimpledrv" peripheral and IRC to GPIO mapping
by Pavel Pisa 01 Jan '18

01 Jan '18

I have answered questions of one group of students in the laboratory where to locate interrupts and signals to process the second "dcsimpledrv" IRC signals in software. The IRC related signals are routed to the Zynq Processing System IP EMIO (GPIO from PL) signals. There is an excerpt from complete document with all signals and registers description which I have provided with the design. Routing of IRC signals to the EMIO GPIO port Mapping is provided by canbench_cc_gpio.vhd GPIO0 IRC1_A GPIO1 IRC1_B GPIO2 IRC1_IRQ (external incoming IRQ signal) GPIO3 IRC1_CGH (10 ns pulse when change is detected by qcounter_nbit.vhdl component) GPIO4 IRC2_A GPIO5 IRC2_B GPIO6 IRC2_IRQ (external incoming IRQ signal) GPIO7 IRC2_CGH (10 ns pulse when change is The important information for processing is that the same GPIO (EMIO) peripheral is used for the first and the second IRC input. This means that the same IRQ vector is/has to be used for both IRC inputs processing in the software. But external signal which notifies hardware about IRC signals state change is fed to GPIO6 for the second IRC instead of GPIO2. This means that bit 6 instead of (or together with) bit 2 has to be monitored and unmasked in Interrupt Enable/Unmask register and all other coresponding locations. Best wishes, Pavel Pisa

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